- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄382641 > TMS320LF2402PZA (Texas Instruments, Inc.) DSP CONTROLLERS PDF資料下載
參數(shù)資料
| 型號(hào)： | TMS320LF2402PZA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | DSP CONTROLLERS |
| 中文描述： | DSP控制器 |
| 文件頁(yè)數(shù)： | 21/115頁(yè) |
| 文件大小： | 1511K |
| 代理商： | TMS320LF2402PZA |
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)當(dāng)前第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)
SPRS094I APRIL 1999 REVISED SEPTEMBER 2003
21
POST OFFICE BOX 1443
HOUSTON, TEXAS 772511443
device reset and interrupts
The TMS320x240x software-programmable interrupt structure supports flexible on-chip and external interrupt
configurations to meet real-time interrupt-driven application requirements. The LF240x recognizes three types of
interrupt sources.
Reset
(hardware- or software-initiated) is unarbitrated by the CPU and takes immediate priority over any
other executing functions. All maskable interrupts are disabled until the reset service routine enables them.
The LF240x devices have two sources of reset: an external reset pin and a watchdog timer time-out (reset).
Hardware-generated interrupts
are requested by external pins or by on-chip peripherals. There are two
types:
External interrupts
are generated by one of four external pins corresponding to the interrupts XINT1,
XINT2, PDPINTA, and PDPINTB. These four can be masked both by dedicated enable bits and by the
CPU’s interrupt mask register (IMR), which can mask each maskable interrupt line at the DSP core.
Peripheral interrupts
are initiated internally by these on-chip peripheral modules: event manager A,
event manager B, SPI, SCI, CAN, and ADC. They can be masked both by enable bits for each event in
each peripheral and by the CPU’s IMR, which can mask each maskable interrupt line at the DSP core.
Software-generated interrupts
for the LF240x devices include:
The INTR instruction.
This instruction allows initialization of any LF240x interrupt with software. Its
operand indicates the interrupt vector location to which the CPU branches. This instruction globally
disables maskable interrupts (sets the INTM bit to 1).
The NMI instruction.
This instruction forces a branch to interrupt vector location 24h. This instruction
globally disables maskable interrupts. 240x devices do not have the NMI hardware signal, only software
activation is provided.
The TRAP instruction.
This instruction forces the CPU to branch to interrupt vector location 22h. The
TRAP instruction does
not
disable maskable interrupts (INTM is not set to 1); therefore, when the CPU
branches to the interrupt service routine, that routine can be interrupted by the maskable hardware
interrupts.
An emulator trap.
This interrupt can be generated with either an INTR instruction or a TRAP instruction.
Six core interrupts (INT1INT6) are expanded using a peripheral interrupt expansion (PIE) module identical to
the F24x devices. The PIE manages all the peripheral interrupts from the 240x peripherals and are grouped to
share the six core level interrupts. Figure 4 shows the PIE block diagram for hardware-generated interrupts.
The PIE block diagram (Figure 4) and the interrupt table (Table 3) explain the grouping and interrupt vector
maps. LF240x devices have interrupts identical to those of the F24x devices and should be completely
code-compatible. 240x devices also have peripheral interrupts identical to those of the F24x plus additional
interrupts for new peripherals such as event manager B. Though the new interrupts share the 24x interrupt
grouping, they all have a unique vector to differentiate among the interrupts. See Table 3 for details.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| TMS320LF2402PZS | DSP CONTROLLERS |
| TMS320LF2407PGA | DSP CONTROLLERS |
| TMS320LF2406PGS | DSP CONTROLLERS |
| TMS320LF2407PZS | DSP CONTROLLERS |
| TMS320LF2407PGS | DSP CONTROLLERS |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS320LF2403APAG4 | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC CMOS 320LF2403 RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320LF2403APAGA | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 16B FixedPt DSP RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
| TMS320LF2403APAGA | 制造商:Texas Instruments 功能描述:16BIT DSP FLASH SMD 320LF2403 |
| TMS320LF2403APAGA | 制造商:Texas Instruments 功能描述:Digital Signal Processor IC Leaded Proce |
| TMS320LF2403APAGS | 功能描述:數(shù)字信號(hào)處理器和控制器 - DSP, DSC 18-Bit Univ Bus Drv With 3-State Outputs RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線(xiàn)寬度:16 bit 程序存儲(chǔ)器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時(shí)鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時(shí)器數(shù)量:3 設(shè)備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風(fēng)格:SMD/SMT |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。