- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄382641 > TMS320LC57PBKA50 16-Bit Digital Signal Processor PDF資料下載
參數(shù)資料
| 型號： | TMS320LC57PBKA50 |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | 16-Bit Digital Signal Processor |
| 中文描述： | 16位數(shù)字信號處理器 |
| 文件頁數(shù)： | 75/87頁 |
| 文件大?。?/td> | 1259K |
| 代理商： | TMS320LC57PBKA50 |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁當前第75頁第76頁第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁
TMS320C5x, TMS320LC5x
DIGITAL SIGNAL PROCESSORS
SPRS030A – APRIL 1995 – REVISED APRIL 1996
75
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
BUFFERED SERIAL-PORT TRANSMIT TIMING OF EXTERNAL FRAMES (SEE NOTES 9 AND 10)
switching characteristics over recommended operating conditions (see Figure 28)
PARAMETER
MIN
MAX
UNIT
td(CXH-DXV)
tdis(CXH-DX)
tdis(CXH-DX)PCM
ten(CXH-DX)PCM
th(CXH-DXV)
Delay time, DX valid after CLKX rising edge
5
21
ns
Disable time, DX invalid after CLKX rising edge
5
15
ns
Disable time in PCM mode, DX invalid after CLKX rising edge
15
ns
Enable time in PCM mode, DX valid after CLKX rising edge
21
ns
Hold time, DX valid after CLKX rising edge
5
20
ns
timing requirements over recommended operating conditions (see Figure 28)
MIN
MAX
UNIT
tc(SCK)
tf(SCK)
tr(SCK)
tw(SCK)
tsu(FX-CXL)
th(CXL-FX)
The serial-port design is fully static and, therefore, can operate with tc(SCK) approaching
∞
. It is characterized approaching an input frequency
of 0 Hz but tested at a much higher frequency to minimize test time.
Values derived from characterization data and not tested
§If the FSX pulse does not meet this specification, the first bit of the serial data is driven on the DX pin until FSX goes low (sampled on falling edge
of CLKX). After falling edge of the FSX, data is shifted out on the DX pin.
NOTE 9: Internal clock with external FSX and vice versa are also allowable. However, FSX timings to CLKX always are defined depending on
the source of FSX, and CLKX timings always are dependent upon the source of CLKX. Specifically, the relationship of FSX to CLKX
is independent of the source of CLKX. External FSX timings are obtained from the “timing requirements over recommended operating
conditions” table listed in the “Buffered Serial-Port Transmit Timing of External Frames” section and internal FSX timings are obtained
from the “switching characteristics over recommended operating conditions” table listed under the “Buffered Serial-Port Transmit Timing
of Internal Frame and Internal Clock” section. Internal CLKX timings are obtained from the “switching characteristics over recommended
operating conditions” table listed under the “Buffered Serial-Port Transmit Timing of Internal Frame and Internal Clock” section and
external CLKX timings are obtained from the “timing requirements over recommended operating conditions” table in the “Buffered
Serial-Port Transmit Timing of External Frames” section.
NOTE 10: Timings for CLKX and FSX are given with polarity bits (CLKP and FSP) set to 0
Cycle time, serial-port clock
25
ns
Fall time, serial-port clock
4
4
ns
Rise time, serial-port clock
ns
Pulse duration, serial-port clock low/high
8.5
ns
Setup time, FSX before CLKX falling edge
5
ns
Hold time, FSX after CLKX falling edge
5
tc(SCK)–5§
ns
DX BIt
FSX
CLKX
8/16
7/15
2
1
th(CXH-DXV)
td(CXH-DXV)
tw(SCK)
tr(SCK)
tf(SCK)
tw(SCK)
tc(SCK)
th(CXL-FX)
tdis(CXH-DX)
tsu(FX-CXL)
Figure 28. Buffered Serial-Port Transmit Timing of External Clocks and External Frames
相關PDF資料 |
PDF描述 |
|---|---|
| TMS320LC57PBKA80 | 16-Bit Digital Signal Processor |
| TMS320LF2407PZA | DSP CONTROLLERS |
| TMS320LF2402PGEA | DSP CONTROLLERS |
| TMS320LF2402PGES | DSP CONTROLLERS |
| TMS320LF2402PZA | DSP CONTROLLERS |
相關代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMS320LF2401AVFA | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC Controller RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| TMS320LF2401AVFS | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16-Bit Fixed-Pt DSP with Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| TMS320LF2402APGA | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16-Bit Fixed-Pt DSP with Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| TMS320LF2402APGAR | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 18-Bit Univ Bus Drv With 3-State Outputs RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
| TMS320LF2402APGS | 功能描述:數(shù)字信號處理器和控制器 - DSP, DSC 16-Bit Fixed-Pt DSP with Flash RoHS:否 制造商:Microchip Technology 核心:dsPIC 數(shù)據(jù)總線寬度:16 bit 程序存儲器大小:16 KB 數(shù)據(jù) RAM 大小:2 KB 最大時鐘頻率:40 MHz 可編程輸入/輸出端數(shù)量:35 定時器數(shù)量:3 設備每秒兆指令數(shù):50 MIPs 工作電源電壓:3.3 V 最大工作溫度:+ 85 C 封裝 / 箱體:TQFP-44 安裝風格:SMD/SMT |
發(fā)布緊急采購，3分鐘左右您將得到回復。