參數(shù)資料
型號(hào)： TMS320LC31PQL
廠商： Texas Instruments, Inc.
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSORS
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 6/48頁(yè)
文件大?。?/td> 652K
代理商： TMS320LC31PQL
TMS320C31, TMS320LC31
DIGITAL SIGNAL PROCESSORS
SPRS035B – MARCH 1996 – REVISED JANUARY 1999
6
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
TMS320C31 and TMS320LC31 Terminal Functions (Continued)
TERMINAL
TYPE
DESCRIPTION
CONDITIONS
WHEN
SIGNAL IS Z TYPE
NAME
QTY
SUPPLY AND OSCILLATOR SIGNALS
H1
1
O/Z
External H1 clock. H1 has a period equal to twice CLKIN.
S
H3
1
O/Z
External H3 clock. H3 has a period equal to twice CLKIN.
S
VDD
20
I
5-V supply for ’C31 devices and 3.3-V supply for ’LC31 devices. All must be
connected to a common supply plane.§
VSS
25
I
Ground. All grounds must be connected to a common ground plane.
X1
1
O
Output from the internal-crystal oscillator. If a crystal is not used, X1 should be left
unconnected.
X2/CLKIN
1
I
Internal-oscillator input from a crystal or a clock
RESERVED
EMU2–EMU0
3
I
Reserved for emulation. Use pullup resistors to VDD
Reserved for emulation
EMU3
I = input, O = output, Z = high-impedance state
S = SHZ active, H = HOLD active, R = RESET active
§Recommended decoupling capacitor value is 0.1
μ
F.
Follow the connections specified for the reserved pins. Use 18-k
–22-k
pullup resistors for best results. All VDD supply pins must be connected
to a common supply plane, and all ground pins must be connected to a common ground plane.
NOTES:
1. A test mode for measuring leakage currents in the TMS320C31 is implemented. This test mode powers down the clock oscillator
circuit resulting in currents below 10
μ
A. The test mode is entered by asserting SHZ low, which tri–states all output pins and then
holds both H1 and H3 at logic high. The test mode is not intended for application use because it does not preserve the processor
state.
2. Since SHZ is a synchronized input and the clock is disabled, exiting the test mode occurs only when at least one of the H1/H3 pins
is pulled low. Reset cannot be used to wake up in test mode since the SHZ pin is sampled and the clocks are not running.
3. On power up, the processor can be in an indeterminate state. If the state is SHZ mode and H1 and H3 are both held logic high by
pull–ups, then shutdown will occur. Normally, if H1 and H3 do not have pull–ups, the rise time lag due to capacitive loading on a
tri–state pin is enough to ensure a clean start. However, a slowly rising supply and board leakages to VCC may be enough to cause
a bad start. Therefore, a pulldown resistor on either H1 or H3 is recommended for proper wakeup.
1
O/Z
S
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