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參數(shù)資料
| 型號： | TMS320LC2402APGES |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP CONTROLLERS |
| 中文描述： | DSP控制器 |
| 文件頁數(shù)： | 110/134頁 |
| 文件大小： | 1759K |
| 代理商： | TMS320LC2402APGES |
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TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145K
JULY 2000
REVISED AUGUST 2005
110
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
Flash parameters @40 MHz CLOCKOUT
PARAMETER
MIN
TYP
MAX
UNIT
μ
s
ms
Time/Word (16-bit)
30
Clear/Programming time
Time/4K Sector
130
Time/12K Sector
400
ms
Erase time
Time/4K Sector
350
ms
Time/12K Sector
1
s
I
CCP
(V
CCP
pin current)
Indicates the typical/maximum current consumption during the
Clear-Erase-Program (C-E-P) cycle
5
15
mA
TI releases upgrades to the Flash algorithms for these devices; hence, these typical values are subject to change.
The indicated time does not include the time it takes to load the C-E-P algorithm and the code (to be programmed) onto on-chip RAM. The values
specified are when V
DD
= 3.3 V and V
CCP
= 5 V, and any deviation from these values could affect the timing parameters. Aging and process variance
could also impact the timing parameters.
migrating from LF240xA (Flash) devices to LC240xA (ROM) devices
When migrating from a Flash to a ROM device, be sure to review this section for a list of important differences
that should be considered. Customer applications should consider these differences in their design, prior to
ROM code submission. Due to the fact that the flash and ROM are different silicon, the following parameters
may be similar but not exactly identical. Refer to the respective datasheet sections for more detail:
EMI/ESD behavior
ADC performance
Current consumption
Device ID register values
Table 18 outlines the differences between the LF240xA (Flash) devices and the LC240xA (ROM) devices.
Table 18. Differences Between LF240xA (Flash) Devices and LC240xA (ROM) Devices
FEATURE
LF2406A
LC2406A
LC2404A
LF2403A
LC2403A
LF2402A
LC2402A
On-chip Flash or ROM
32K
32K
16K
16K
16K
8K
6K
Single-Access RAM (SARAM)
(16-bit words)
2K
2K
1K
512
512
512
—
Boot ROM
Yes
—
—
Yes
Yes
Yes
—
Event Managers
EVA, EVB
EVA, EVB
EVA, EVB
EVA
EVA
EVA
EVA
ADC Channels
16
16
16
8
8
8
8
SPI
Yes
Yes
Yes
Yes
§
Yes
§
—
—
CAN
Yes
Yes
—
Yes
Yes
—
—
GPIO Pins
41
41
41
21
21
21
21
BIO Pin
Yes
Yes
Yes
—
—
—
—
TDIRx Pin
Yes
Yes
Yes
—
—
—
—
External Interrupts
Access to External Memory Spaces
5
5
5
3
3
3
3
See Note 1
See Note 2
See Note 2
See Note 1
See Note 1
See Note 1
See Note 2
V
CCP
Pin Functionality
V
CCP
100-pin
PZ
No Connect
No Connect
V
CCP
64-pin
PAG
No Connect
V
CCP
64-pin
PG
No Connect
Packaging
100-pin
PZ
100-pin
PZ
64-pin
PAG
64-pin
PG, PAG
§
The SPISTE pin is not available on the LF2403A. See the SPI Slave Mode Operation in LF2403A section.
Application code should
NOT
access Illegal/Reserved addresses.
NOTES:
1. Access to external Program, Data, and I/O space is considered illegal and would assert an NMI.
2. The external Program and I/O spaces are implemented as “reserved” addresses and any access will not assert an NMI. However,
the external data memory space is illegal.
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