參數(shù)資料
型號(hào): TMS320LC2401APGA
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: DSP CONTROLLERS
中文描述: DSP控制器
文件頁數(shù): 80/134頁
文件大?。?/td> 1759K
代理商: TMS320LC2401APGA
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145K
JULY 2000
REVISED AUGUST 2005
80
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
external reference crystal/clock with PLL circuit enabled
timing parameters with the PLL circuit enabled
PARAMETER
MIN
MAX
UNIT
Resonator
4
13
f
x
Input clock frequency
Crystal
4
20
MHz
CLKIN
4
20
Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.
switching characteristics over recommended operating conditions [H = 0.5 t
c(CO)
] (see Figure 26)
PARAMETER
PLL MODE
MIN
TYP
MAX
UNIT
t
c(CO)
t
f(CO)
t
r(CO)
t
w(COL)
t
w(COH)
Cycle time, CLKOUT
×
4 mode
25
ns
Fall time, CLKOUT
4
ns
Rise time, CLKOUT
4
ns
Pulse duration, CLKOUT low
H
3
H
H+3
ns
Pulse duration, CLKOUT high
H
3
H
H+3
ns
t
t
Transition time, PLL synchronized after RS pin high
4096t
c(Cl)
ns
Input frequency should be adjusted (CLK PS bits in SCSR1 register) such that CLKOUT = 40 MHz maximum, 4 MHz minimum.
timing requirements (see Figure 26)
MIN
MAX
UNIT
t
c(Cl)
t
f(Cl)
t
r(Cl)
t
w(CIL)
t
w(CIH)
Cycle time, XTAL1/CLKIN
250
ns
Fall time, XTAL1/CLKIN
5
ns
Rise time, XTAL1/CLKIN
5
ns
Pulse duration, XTAL1/CLKIN low as a percentage of t
c(Cl)
Pulse duration, XTAL1/CLKIN high as a percentage of t
c(Cl)
40
60
%
40
60
%
XTAL1/CLKIN
t
c(CI)
t
w(CIL)
t
w(CIH)
t
f(Cl)
t
r(Cl)
t
c(CO)
t
w(COH)
t
w(COL)
t
r(CO)
t
f(CO)
CLKOUT
Figure 26. CLKIN-to-CLKOUT Timing with PLL and External Clock in
×
4 Mode
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