參數(shù)資料
型號： TMS320F28069UPZT
廠商： Texas Instruments
文件頁數(shù)： 107/174頁
文件大?。?/td> 0K
描述： IC MCU 32BIT 256KB FLASH 100LQFP
產(chǎn)品培訓(xùn)模塊： ControlSUITE
Piccolo F2806x
TPS75005 Single IC Power for C2000 MCU
標(biāo)準(zhǔn)包裝： 90
系列： TMS320F2806x, Piccolo™, C2000™
核心處理器： C28x
芯體尺寸： 32-位
速度： 80MHz
連通性： CAN，I²C，McBSP，SCI，SPI，UART/USART
外圍設(shè)備： 欠壓檢測/復(fù)位，DMA，POR，PWM，WDT
輸入/輸出數(shù)： 54
程序存儲器容量： 256KB（128K x 16）
程序存儲器類型： 閃存
RAM 容量： 50K x 16
電壓 - 電源 (Vcc/Vdd)： 1.71 V ~ 1.995 V
數(shù)據(jù)轉(zhuǎn)換器： A/D 16x12b
振蕩器型： 內(nèi)部
工作溫度： -40°C ~ 105°C
封裝/外殼： 100-LQFP
包裝： 托盤
SPRS698D – NOVEMBER 2010 – REVISED DECEMBER 2012
2.5.20 32-Bit CPU-Timers (0, 1, 2)
CPU-Timers 0, 1, and 2 are identical 32-bit timers with presettable periods and with 16-bit clock
prescaling. The timers have a 32-bit count-down register, which generates an interrupt when the counter
reaches zero. The counter is decremented at the CPU clock speed divided by the prescale value setting.
When the counter reaches zero, it is automatically reloaded with a 32-bit period value.
CPU-Timer 0 is for general use and is connected to the PIE block. CPU-Timer 1 is also for general use
and can be connected to INT13 of the CPU. CPU-Timer 2 is reserved for DSP/BIOS. CPU-Timer 2 is
connected to INT14 of the CPU. If DSP/BIOS is not being used, CPU-Timer 2 is available for general use.
CPU-Timer 2 can be clocked by any one of the following:
SYSCLKOUT (default)
Internal zero-pin oscillator 1 (INTOSC1)
Internal zero-pin oscillator 2 (INTSOC2)
External clock source
2.5.21 Control Peripherals
The devices support the following peripherals that are used for embedded control and communication:
ePWM:
The enhanced PWM peripheral supports independent/complementary PWM
generation, adjustable dead-band generation for leading/trailing edges,
latched/cycle-by-cycle trip mechanism. Some of the PWM pins support the
HRPWM high resolution duty and period features. The type 1 module found on
2806x devices also supports increased dead-band resolution, enhanced SOC and
interrupt generation, and advanced triggering including trip functions based on
comparator outputs.
eCAP:
The enhanced capture peripheral uses a 32-bit time base and registers up to four
programmable events in continuous/one-shot capture modes.
This peripheral can also be configured to generate an auxiliary PWM signal.
eQEP:
The enhanced QEP peripheral uses a 32-bit position counter, supports low-speed
measurement using capture unit and high-speed measurement using a 32-bit unit
timer. This peripheral has a watchdog timer to detect motor stall and input error
detection logic to identify simultaneous edge transition in QEP signals.
ADC:
The ADC block is a 12-bit converter. The ADC has up to 16 single-ended channels
pinned out, depending on the device. The ADC also contains two sample-and-hold
units for simultaneous sampling.
Comparator:
Each comparator block consists of one analog comparator along with an internal
10-bit reference for supplying one input of the comparator.
HRCAP:
The high-resolution capture peripheral operates in normal capture mode via a 16-
bit counter clocked off of the HCCAPCLK or in high-resolution capture mode by
utilizing built-in calibration logic in conjunction with a TI-supplied calibration library.
38
Device Overview
Copyright 2010–2012, Texas Instruments Incorporated
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