參數(shù)資料
型號(hào): TMS320F28044_07
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: Digital Signal Processor
中文描述: 數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 62/107頁(yè)
文件大?。?/td> 784K
代理商: TMS320F28044_07
www.ti.com
4.9
GPIO MUX
GPxDAT (read)
Input
Qualification
GPxMUX1/2
High Impedance
Output Control
GPIOx pin
XRS
0 = Input, 1 = Output
Low Power
Modes Block
GPxDIR (latch)
Peripheral 2 Input
Peripheral 3 Input
Peripheral 1 Output
Peripheral 2 Output
Peripheral 3 Output
Peripheral 1 Output Enable
Peripheral 2 Output Enable
Peripheral 3 Output Enable
00
01
10
11
00
01
10
11
00
01
10
11
GPxCTRL
Peripheral 1 Input
N/C
GPxPUD
LPMCR0
Internal
Pullup
GPIOLMPSEL
GPxQSEL1/2
GPxSET
GPxDAT (latch)
GPxCLEAR
GPxTOGGLE
GPIOXINT1SEL
GPIOXINT2SEL
GPIOXNMISEL
= Default at Reset
PIE
External Interrupt
MUX
Asynchronous
path
Asynchronous path
TMS320F28044
Digital Signal Processor
SPRS357B–AUGUST 2006–REVISED MAY 2007
On the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO
pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin
is shown in
Figure 4-11
. Because of the open drain capabilities of the I
2
C pins, the GPIO MUX block
diagram for these pins differ. See the
TMS320x280x, 2801x, 2804x System Control and Interrupts
Reference Guide
(literature number
SPRU712
) for details.
A.
x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register
depending on the particular GPIO pin selected.
GPxDAT latch/read are accessed at the same memory location.
B.
Figure 4-11. GPIO MUX Block Diagram
Peripherals
62
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