參數(shù)資料
型號(hào)： TMS320C6712GHK100
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： FIXED-POINT DIGITAL SIGNAL PROCESSOR
中文描述： 定點(diǎn)數(shù)字信號(hào)處理器
文件頁數(shù)： 42/70頁
文件大?。?/td> 1050K
代理商： TMS320C6712GHK100
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E
OCTOBER 1999
REVISED MARCH 2004
42
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
SYNCHRONOUS DRAM TIMING
timing requirements for synchronous DRAM cycles (see Figure 21)
NO.
200
UNIT
MIN
1.25
MAX
7
8
t
su(EDV-CKO2H)
t
h(CKO2H-EDV)
Setup time, read EDx valid before CLKOUT2 high
Hold time, read EDx valid after CLKOUT2 high
ns
ns
3
switching characteristics over recommended operating conditions for synchronous DRAM
cycles
(see Figure 21
Figure 26)
NO.
PARAMETER
200
UNIT
MIN
P
1
P
3.5
P
1
P
3.5
P
1
P
3.5
P
1
P
3.5
P
3
P
3.5
P
1
P
3.5
P
1
P
3.5
P
1
P
3.5
MAX
1
2
3
4
5
6
9
10
11
12
13
14
15
16
17
18
t
osu(CEV-CKO2H)
t
oh(CKO2H-CEV)
t
osu(BEV-CKO2H)
t
oh(CKO2H-BEIV)
t
osu(EAV-CKO2H)
t
oh(CKO2H-EAIV)
t
osu(CASV-CKO2H)
t
oh(CKO2H-CASV)
t
osu(EDV-CKO2H)
t
oh(CKO2H-EDIV)
t
osu(WEV-CKO2H)
t
oh(CKO2H-WEV)
t
osu(SDA10V-CKO2H)
t
oh(CKO2H-SDA10IV)
t
osu(RASV-CKO2H)
t
oh(CKO2H-RASV)
Output setup time, CEx valid before CLKOUT2 high
Output hold time, CEx valid after CLKOUT2 high
Output setup time, BEx valid before CLKOUT2 high
Output hold time, BEx invalid after CLKOUT2 high
Output setup time, EAx valid before CLKOUT2 high
Output hold time, EAx invalid after CLKOUT2 high
Output setup time, SDCAS/SSADS valid before CLKOUT2 high
Output hold time, SDCAS/SSADS valid after CLKOUT2 high
Output setup time, EDx valid before CLKOUT2 high
§
Output hold time, EDx invalid after CLKOUT2 high
Output setup time, SDWE/SSWE valid before CLKOUT2 high
Output hold time, SDWE/SSWE valid after CLKOUT2 high
Output setup time, SDA10 valid before CLKOUT2 high
Output hold time, SDA10 invalid after CLKOUT2 high
Output setup time, SDRAS/SSOE valid before CLKOUT2 high
Output hold time, SDRAS/SSOE valid after CLKOUT2 high
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
SDCAS/SSADS, SDRAS/SSOE, and SDWE/SSWE operate as SDCAS, SDRAS, and SDWE, respectively, during SDRAM accesses.
§
For the first write in a series of one or more consecutive adjacent writes, the write data is generated one CLKOUT2 cycle early to accommodate
the ED enable time.
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