參數(shù)資料
型號: TMS320C6701GLS100
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSOR
中文描述: 定點數(shù)字信號處理器
文件頁數(shù): 35/70頁
文件大小: 1050K
代理商: TMS320C6701GLS100
TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E
OCTOBER 1999
REVISED MARCH 2004
35
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
INPUT AND OUTPUT CLOCKS
timing requirements for CLKIN
§
(see Figure 12)
200
NO.
PLL mode x4,
x6, x7, x8, x9,
x10, x11
PLL mode
x1
UNIT
MIN
5 * M
0.4C
0.4C
MAX
MIN
5
0.45C
0.45C
MAX
1
2
3
4
t
c(CLKIN)
t
w(CLKINH)
t
w(CLKINL)
t
t(CLKIN)
Cycle time, CLKIN
Pulse duration, CLKIN high
Pulse duration, CLKIN low
Transition time, CLKIN
ns
ns
ns
ns
5
0.6
The reference points for the rise and fall transitions are measured at V
IL
MAX and V
IH
MIN.
M = the PLL multiplier factor (x4, x6, x7, x8, x9, x10, or x11). For more details, see the clock PLL section of this data sheet.
§
C = CLKIN cycle time in ns. For example, when CLKIN frequency is 50 MHz, use C = 20 ns.
CLKIN
1
2
3
4
4
Figure 12. CLKIN Timings
timing requirements for PCLKIN
(see Figure 13)
NO.
200
UNIT
MIN
30
11
11
MAX
1
2
3
4
t
c(PCLK)
t
w(PCLKH)
t
w(PCLKL)
t
sr(PCLK)
Cycle time, PCLK
Pulse duration, PCLK high
Pulse duration, PCLK low
v/
t slew rate, PCLK
ns
ns
ns
V/ns
1
4
When the 5-V PCI clamp is used, the reference points for the rise and fall transitions are measured V
ILP
MAX and V
IHP
MIN for 5 V operation.
When the 3.3-V PCI clamp is used, the reference points for the rise and fall transitions are measured at V
ILP
MAX and V
IHP
MIN for 3.3 V
operation.
PCLK
1
2
3
4
4
2 V MIN
Peak to Peak for
5V signaling
or
0.4 V
MIN
Peak to Peak for
3V signaling
Figure 13. PCLK Timings
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