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參數(shù)資料
| 型號： | TMS320C6701GJL100 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 定點數(shù)字信號處理器 |
| 文件頁數(shù)： | 47/70頁 |
| 文件大小： | 1050K |
| 代理商： | TMS320C6701GJL100 |
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E
OCTOBER 1999
REVISED MARCH 2004
47
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
RESET TIMING
timing requirements for reset (see Figure 28)
NO.
200
UNIT
MIN
10P
250
5P
#
5P
MAX
1
t
w(RST)
Width of the RESET pulse (PLL stable)
Width of the RESET pulse (PLL needs to sync up)
§
Setup time, ED boot configuration bits valid before RESET high
Hold time, ED boot configuration bits valid after RESET high
This parameter applies to CLKMODE x1 when CLKIN is stable, and applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 when CLKIN and PLL
are stable.
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
§
This parameter applies to CLKMODE x4, x6, x7, x8, x9, x10, and x11 only. The RESET signal is not connected internally to the Clock PLL circuit.
The PLL requires a minimum of 250
μ
s to stabilize following device power up or after PLL configuration has been changed. During that time,
RESET must be asserted to ensure proper device operation. See the
clock PLL
section for power up (specifically Figure 5, Note E) and for PLL
lock times (Table 4).
ED[31:0] are the boot configuration pins during device reset.
#
A 250
μ
s setup time before the rising edge of RESET is required when using CLKMODE x4, x6, x7, x8, x9, x10, or x11.
ns
μ
s
ns
ns
10
11
t
su(ED)
t
h(ED)
switching characteristics over recommended operating conditions during reset
||
(see Figure 28)
NO.
PARAMETER
200
UNIT
MIN
MAX
2
3
4
5
6
7
8
9
t
d(RSTL-CKO2IV)
t
d(RSTH-CKO2V)
t
d(RSTL-HIGHIV)
t
d(RSTH-HIGHV)
t
d(RSTL-LOWIV)
t
d(RSTH-LOWV)
t
d(RSTL-ZHZ)
t
d(RSTH-ZV)
Delay time, RESET low to CLKOUT2 invalid
Delay time, RESET high to CLKOUT2 valid
Delay time, RESET low to high group invalid
Delay time, RESET high to high group valid
Delay time, RESET low to low group invalid
Delay time, RESET high to low group valid
Delay time, RESET low to Z group high impedance
Delay time, RESET high to Z group valid
P
ns
ns
ns
ns
ns
ns
ns
ns
4P
P
4P
P
4P
P
4P
P = 1/CPU clock frequency in ns. For example, when running parts at 200 MHz, use P = 5 ns.
||
High group consists of:
HOLDA
Low group consists of:
IACK, INUM[3:0], DMAC[3:0], PD, TOUT0, and TOUT1, XSP_CLK, XSP_DO, and XSP_CS
Z group consists of:
EA[21:2], ED[31:0], CE[3:0], BE[3:0], ARE, AWE, AOE, SDCAS/SSADS, SDRAS/SSOE, SDWE/SSWE,
SDA10, CLKX0, CLKX1, FSX0, FSX1, DX0, DX1, CLKR0, CLKR1, FSR0, FSR1, AD[31:0],
PCBE[3:0], PINTA, PREQ, PSERR, PPERR, PDEVSEL, PFRAME, PIRDY, PPAR, PSTOP, PTRDY, and PME
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