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參數(shù)資料
| 型號： | TMS320C6414GLW100 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 定點數(shù)字信號處理器 |
| 文件頁數(shù)： | 27/70頁 |
| 文件大?。?/td> | 1050K |
| 代理商： | TMS320C6414GLW100 |
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TMS320C6205
FIXED-POINT DIGITAL SIGNAL PROCESSOR
SPRS106E
OCTOBER 1999
REVISED MARCH 2004
27
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
clock PLL (continued)
Table 3. C6205 PLL Multiply Modes and x1 (Bypass) Options
CLKMODE0
ED[31]
ED[27]
ED[23]
PLL MULTIPLY
FACTORS
CPU CLOCK FREQ
f(CPU clock)
0
1
1
1
1
1
1
1
1
X
0
0
0
0
1
1
1
1
X
0
0
1
1
0
0
1
1
X
0
1
0
1
0
1
0
1
x1 (Bypass)
x1 (Bypass)
x4
x8
x10
x6
x9
x7
x11
1
×
f
(CLKIN)
1
×
f
(CLKIN)
4
×
f
(CLKIN)
8
×
f
(CLKIN)
10
×
f
(CLKIN)
6
×
f
(CLKIN)
9
×
f
(CLKIN)
7
×
f
(CLKIN)
11
×
f
(CLKIN)
CLKMODE0 equal to 0 denotes on-chip PLL bypassed
CLKMODE0 equal to 1 denotes on-chip PLL used, except when configuration bits (ED[31], ED[27], and
ED[23]) are 0 at device reset.
ED[31], ED[27], and ED[23] are the on-chip PLL configuration bits that are latched during device reset,
along with the other boot configuration bits ED[31:0].
Table 4. C6205 PLL Component Selection Table
§
CLKMODE
CLKIN
RANGE
(MHZ)
CPU CLOCK
FREQUENCY
(CLKOUT1)
RANGE (MHZ)
CLKOUT2
RANGE
(MHZ)
R1 [ 1%]
( )
C1 [ 10%]
(NF)
C2 [ 10%]
(PF)
TYPICAL
LOCK TIME
( S)
x4
x6
x7
x8
x9
x10
x11
32.5
50
21.7
33.3
18.6
28.6
16.3
25
14.4
22.2
13
20
11.8
18.2
130 200
65 100
60.4
27
560
75
§
Under some operating conditions, the maximum PLL lock time may vary as much as 150% from the specified typical value. For example, if the
typical lock time is specified as 100
μ
s, the maximum value may be as long as 250
μ
s.
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