參數(shù)資料
型號(hào)： TMS320AV110
廠商： Texas Instruments, Inc.
英文描述： MPEG Audio Decoder(MPEG音頻譯碼器)
中文描述： MPEG音頻解碼器（的MPEG音頻譯碼器）
文件頁(yè)數(shù)： 11/38頁(yè)
文件大?。?/td> 796K
代理商： TMS320AV110
TMS320AV110
MPEG AUDIO DECODER
SCSS013C – MAY 1993 – REVISED AUGUST 1995
11
POST OFFICE BOX 655303
DALLAS, TEXAS 75265
byte-parallel data input
Byte-parallel data input is performed using the data I/Os (SDATA[7:0]) and the data strobe (DSTRB) input. Data
is strobed into the chip on the rising edge of DSTRB. REQ goes high after every rising edge of DSTRB. REQ
remains high only when the input buffer is full (see Figure 3). One additional byte of data can be input after REQ
signals that the input buffer is full. REQ returns low synchronous to the system clock (OSCIN) when the ’AV110
is ready for more data.
’AV110 CONTROL REGISTER
SIN EN
SIN_EN
Serial input enable
0 = Parallel (byte) data input (see Figure 3)
1 = Serial (bit) data input (see Figure 2)
REQ
SDATA
(7:0)
DSTRB
O
I
tsu1
tsu3
tw1
th2
1/fclock
tpd1
Input buffer is full
Data can be input
Figure 3. Byte-Parallel Data-Input Timing
memory mapped byte-parallel data input
Memory mapped byte-parallel data input is performed as a register access to the primary data-input register
(DATAIN[7:0]). This procedure is described in the following section. REQ goes high on the falling edge of DCS
whenever the DATAIN register is addressed. REQ remains high when the input buffer is full (see Figure 4). One
additional byte of data can be input after REQ signals that the input buffer is full. REQ returns low synchronous
to the system clock (OSCIN) when the device is ready for more data.
access to control and status registers
A register access chip select (DCS) and a seven-bit address (SADDR[6:0]) are used to address the ’AV110
control and status registers including the data-input register. Read/write operations are designated with R/W.
Register access is performed utilizing the chip select, read/write, data, and address lines. The host first sets up
the address, read/write, and data inputs. The DCS line is then asserted by the host. When R/W is high (read),
assertion of the DCS line drives the SDATA lines. For R/W low (write), the ’AV110 latches the data on the SDATA
I/O lines when DCS is deasserted.
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