參數(shù)資料
型號(hào)： TMS28F004AMB70CDBJL
廠商： Texas Instruments, Inc.
英文描述： 524288 BY 8-BIT/262144 BY 16-BIT AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
中文描述： 524288按8-BIT/262144由16位自動(dòng)選擇啟動(dòng)塊閃存
文件頁(yè)數(shù)： 65/80頁(yè)
文件大?。?/td> 1080K
代理商： TMS28F004AMB70CDBJL
TMS28F004Axy, TMS28F400Axy
524288 BY 8-BIT/
262
144 BY 16-BIT
AUTO-SELECT BOOT-BLOCK FLASH MEMORIES
SMJS829A – JANUARY 1996 – REVISED AUGUST 1997
65
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
switching characteristics for TMS28F004AZy and TMS28F400AZy over recommended ranges of
supply voltage (commercial and extended temperature ranges)
read operations
ALT.
’28F004AZy60
’28F400AZy60
’28F004AZy70
’28F400AZy70
’28F004AZy80
’28F400AZy80
PARAMETER
SYMBOL
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
ta(A)
ta(E)
ta(G)
tc(R)
td(E)
td(G)
tdis(E)
tdis(G)
Access time from A0–A17 (see Note 15)
tAVQV
tELQV
tGLQV
tAVAV
tELQX
tGLQX
tEHQZ
tGHQZ
60
70
80
ns
Access time from E
60
70
80
ns
Access time from G
35
40
40
ns
Cycle time, read
60
70
80
ns
Delay time, E low to low-impedance output
0
0
0
ns
Delay time, G low to low-impedance output
0
0
0
ns
Disable time, E to high-impedance output
25
30
30
ns
Disable time, G to high-impedance output
25
30
30
ns
th(D)
Hold time, DQ valid from A0–A17, E, or G,
whichever occurs first (see Note 15)
tAXQX
0
0
0
ns
tsu(EB)
Setup time, BYTE from E low
tELFL
tELFH
tPHQV
5
5
5
ns
td(RP)
Output delay time from RP high
450
450
450
ns
tdis(BL)
Disable time, BYTE low to DQ8–DQ15 in
high-impedance state
tFLQZ
25
30
30
ns
ta(BH)
NOTE 15: A–1–A17 for byte-wide
Access time from BYTE going high
tFHQV
60
70
80
ns
switching characteristics for TMS28F400AZy over recommended ranges of supply voltage
(automotive temperature range)
read operations
ALT.
’28F004AZy70
’28F400AZy70
’28F004AZy80
’28F400AZy80
’28F004AZy90
’28F400AZy90
PARAMETER
SYMBOL
5-V VCC
RANGE
5-V VCC
RANGE
5-V VCC
RANGE
UNIT
MIN
MAX
MIN
MAX
MIN
MAX
ta(A)
ta(E)
ta(G)
tc(R)
td(E)
td(G)
tdis(E)
tdis(G)
Access time from A0–A17 (see Note 15)
tAVQV
tELQV
tGLQV
tAVAV
tELQX
tGLQX
tEHQZ
tGHQZ
70
80
90
ns
Access time from E
70
80
90
ns
Access time from G
35
40
45
ns
Cycle time, read
70
80
90
ns
Delay time, E low to low-impedance output
0
0
0
ns
Delay time, G low to low-impedance output
0
0
0
ns
Disable time, E to high-impedance output
25
30
35
ns
Disable time, G to high-impedance output
25
30
35
ns
th(D)
Hold time, DQ valid from A0–A17, E, or G,
whichever occurs first (see Note 15)
tAXQX
0
0
0
ns
tsu(EB)
Setup time, BYTE from E low
tELFL
tELFH
5
5
5
ns
NOTE 15: A–1–A17 for byte-wide
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