參數(shù)資料
型號： TMR320F2812ZHHA
廠商： Texas Instruments, Inc.
英文描述： MAGNIFIER W/CURVED TWEEZER TIP
中文描述： TMS320R2811，TMS320R2812數(shù)字信號處理器
文件頁數(shù)： 116/147頁
文件大?。?/td> 2021K
代理商： TMR320F2812ZHHA
Electrical Specifications
116
June 2004
SPRS257
6.23
External Interface Read Timing
Table 6
26. External Memory Interface Read Switching Characteristics
PARAMETER
MIN
MAX
UNIT
t
d(XCOH-XZCSL)
t
d(XCOHL-XZCSH)
t
d(XCOH-XA)
t
d(XCOHL-XRDL)
t
d(XCOHL-XRDH
t
h(XA)XZCSH
t
h(XA)XRD
During inactive cycles, the XINTF address bus will always hold the last address put out on the bus. This includes alignment cycles.
Table 6
27. External Memory Interface Read Timing Requirements
Delay time, XCLKOUT high to zone chip-select active low
Delay time, XCLKOUT high/low to zone chip-select inactive high
Delay time, XCLKOUT high to address valid
Delay time, XCLKOUT high/low to XRD active low
Delay time, XCLKOUT high/low to XRD inactive high
Hold time, address valid after zone chip-select inactive high
1
3
2
1
1
ns
ns
ns
ns
ns
ns
2
2
Hold time, address valid after XRD inactive high
ns
MIN
MAX
UNIT
t
a(A)
t
a(XRD)
t
su(XD)XRD
t
h(XD)XRD
LR = Lead period, read access. AR = Active period, read access. See Table 6
24.
Access time, read data from address valid
Access time, read data valid from XRD active low
Setup time, read data valid before XRD strobe inactive high
Hold time, read data valid after XRD inactive high
(LR + AR)
14
AR
12
ns
ns
ns
ns
12
0
Lead
Active
Trail
DIN
t
d(XCOHL-XRDL)
t
d(XCOH-XA)
t
d(XCOH-XZCSL)
t
d(XCOHL-XRDH)
t
h(XD)XRD
t
d(XCOHL-XZCSH)
XCLKOUT=XTIMCLK
XCLKOUT=1/2 XTIMCLK
XZCS0AND1, XZCS2,
XZCS6AND7
XA[0:18]
XRD
XWE
XR/W
XD[0:15]
NOTES: A. All XINTF accesses (lead period) begin on the rising edge of XCLKOUT. When necessary, the device will insert an
alignment cycle before an access to meet this requirement.
B. During alignment cycles, all signals will transition to their inactive state.
C. For USEREADY = 0, the external XREADY input signal is ignored.
D. XA[0:18] will hold the last address put on the bus during inactive cycles, including alignment cycles.
t
su(XD)XRD
t
a(A)
t
a(XRD)
XREADY
Figure 6
26. Example Read Access
XTIMING register parameters used for this example:
XRDLEAD
XRDACTIVE
XRDTRAIL
USEREADY
X2TIMING
XWRLEAD
N/A
XWRACTIVE
N/A
XWRTRAIL
N/A
READYMODE
N/A
≥
1
≥
0
≥
0
0
0
N/A = “Don’t care” for this example
A
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