參數(shù)資料
型號(hào)： TMR320F2812PBKS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述： TMS320R2811，TMS320R2812數(shù)字信號(hào)處理器
文件頁數(shù)： 136/147頁
文件大?。?/td> 2021K
代理商： TMR320F2812PBKS
Electrical Specifications
136
June 2004
SPRS257
Table 6
44. McBSP Switching Characteristics
NO.
M1
M2
M3
PARAMETER
MIN
2P
D-5
§
C-5
§
MAX
UNIT
ns
ns
ns
ns
ns
t
c(CKRX)
t
w(CKRXH)
t
w(CKRXL)
Cycle time, CLKR/X
Pulse duration, CLKR/X high
Pulse duration, CLKR/X low
CLKR/X int
CLKR/X int
CLKR/X int
CLKR int
CLKR ext
CLKX int
CLKX ext
CLKX int
CLKX ext
CLKX int
CLKX ext
D+5
§
C+5
§
M4
t
d(CKRH-FRV)
Delay time CLKR high to internal FSR valid
Delay time, CLKR high to internal FSR valid
0
3
0
3
4
27
4
27
8
14
9
28
M5
t
d(CKXH-FXV)
Delay time CLKX high to internal FSX valid
Delay time, CLKX high to internal FSX valid
ns
M6
t
dis(CKXH-DXHZ)
Disable time, CLKX high to DX high impedance
following last data bit
ns
Delay time, CLKX high to DX valid.
This applies to all bits except the first bit transmitted.
DXENA 0
DXENA = 0
CLKX int
8
M7
t
d(CKXH-DXV)
Delay time, CLKX high to DX valid
CLKX ext
14
ns
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY=01b or 10b) modes
DXENA 1
DXENA = 1
CLKX int
P + 8
CLKX ext
P + 14
DXENA 0
DXENA = 0
CLKX int
0
M8
t
en(CKXH-DX)
Enable time, CLKX high to DX driven
CLKX ext
6
ns
Only applies to first bit transmitted when in Data
Delay 1 or 2 (XDATDLY=01b or 10b) modes
DXENA 1
DXENA = 1
CLKX int
P
CLKX ext
P + 6
DXENA 0
DXENA = 0
FSX int
8
M9
t
d(FXH-DXV)
Delay time, FSX high to DX valid
FSX ext
14
ns
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY=00b) mode.
DXENA 1
DXENA = 1
FSX int
P + 8
FSX ext
P + 14
DXENA 0
DXENA = 0
FSX int
0
M10
t
en(FXH-DX)
Enable time, FSX high to DX driven
FSX ext
6
ns
Only applies to first bit transmitted when in Data
Delay 0 (XDATDLY=00b) mode
DXENA 1
DXENA = 1
FSX int
P
FSX ext
P + 6
Polarity bits CLKRP = CLKXP = FSRP = FSXP = 0. If the polarity of any of the signals is inverted, then the timing references of
that signal are
also inverted.
2P = 1/CLKG in ns.
§
C=CLKRX low pulse width = P
D=CLKRX high pulse width = P
A
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