參數(shù)資料
型號(hào): TMR320F2812GHHQ
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號(hào)處理
英文描述: TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述: TMS320R2811,TMS320R2812數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 21/147頁(yè)
文件大?。?/td> 2021K
代理商: TMR320F2812GHHQ
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Introduction
21
June 2004
SPRS257
Table 2
2. Signal Descriptions
(Continued)
NAME
DESCRIPTION
PU/PD
§
I/O/Z
PIN NO.
128-PIN
PBK
176-PIN
PGF
179-PIN
GHH
AND
ZHH
JTAG
TRST
B12
135
98
I
PD
JTAG test reset with internal pulldown. TRST, when driven
high, gives the scan system control of the operations of the
device. If this signal is not connected or driven low, the device
operates in its functional mode, and the test reset signals are
ignored.
NOTE: Do not use pullup resistors on TRST; it has an internal
pulldown device. In a low-noise environment, TRST can be
left floating. In a high-noise environment, an additional
pulldown resistor may be needed. The value of this resistor
should be based on drive strength of the debugger pods
applicable to the design. A 2.2-k
resistor generally offers
adequate protection. Since this is application-specific, it is
recommended that each target board is validated for proper
operation of the debugger and the application.
TCK
A12
136
99
I
PU
JTAG test clock with internal pullup
JTAG test-mode select (TMS) with internal pullup. This serial
control input is clocked into the TAP controller on the rising
edge of TCK.
TMS
D13
126
92
I
PU
TDI
C13
131
96
I
PU
JTAG test data input (TDI) with internal pullup. TDI is clocked
into the selected register (instruction or data) on a rising edge
of TCK.
TDO
D12
127
93
O/Z
JTAG scan out, test data output (TDO). The contents of the
selected register (instruction or data) is shifted out of TDO on
the falling edge of TCK.
EMU0
D11
137
100
I/O/Z
PU
Emulator pin 0. When TRST is driven high, this pin is used
as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan.
EMU1
C9
146
105
I/O/Z
PU
Emulator pin 1. When TRST is driven high, this pin is used
as an interrupt to or from the emulator system and is
defined as input/output through the JTAG scan.
ADC ANALOG INPUT SIGNALS
I
I
I
I
I
I
I
I
ADCINA7
ADCINA6
ADCINA5
ADCINA4
ADCINA3
ADCINA2
ADCINA1
ADCINA0
Typical drive strength of the output buffer for all pins is 4 mA except for TDO, XCLKOUT, XF, XINTF, EMU0, and EMU1 pins, which are 8 mA.
I = Input, O = Output, Z = High impedance
§
PU = pin has internal pullup; PD = pin has internal pulldown
B5
D5
E5
A4
B4
C4
D4
A3
167
168
169
170
171
172
173
174
119
120
121
122
123
124
125
126
8-Channel analog inputs for Sample-and-Hold A. The ADC
pins should not be driven before V
DDA1
, V
DDA2
, and V
DDAIO
pins have been fully powered up.
A
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