參數(shù)資料
型號： TMR320F2811PBKA
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述： TMS320R2811，TMS320R2812數(shù)字信號處理器
文件頁數(shù)： 112/147頁
文件大小： 2021K
代理商： TMR320F2811PBKA
Electrical Specifications
112
June 2004
SPRS257
6.21
External Interface (XINTF) Timing
Each XINTF access consists of three parts: Lead, Active, and Trail. The user configures the Lead/Active/Trail
wait states in the XTIMING registers. There is one XTIMING register for each XINTF zone. Table 6
24 shows
the relationship between the parameters configured in the XTIMING register and the duration of the pulse in
terms of XTIMCLK cycles.
Table 6
24. Relationship Between Parameters Configured in XTIMING and Duration of Pulse
DESCRIPTION
DURATION (ns)
X2TIMING = 0
XRDLEAD x t
c(XTIM)
(XRDACTIVE + WS + 1) x t
c(XTIM)
XRDTRAIL x t
c(XTIM)
XWRLEAD x t
c(XTIM)
(XWRACTIVE + WS + 1) x t
c(XTIM)
XWRTRAIL x t
c(XTIM)
X2TIMING = 1
(XRDLEAD x 2) x t
c(XTIM)
(XRDACTIVE x 2 + WS + 1) x t
c(XTIM)
(XRDTRAIL x 2) x t
c(XTIM)
(XWRLEAD x 2) x t
c(XTIM)
(XWRACTIVE x 2 + WS + 1) x t
c(XTIM)
(XWRTRAIL x 2) x t
c(XTIM)
LR
AR
TR
LW
AW
TW
Lead period, read access
Active period, read access
Trail period, read access
Lead period, write access
Active period, write access
Trail period, write access
t
c(XTIM)
Cycle time, XTIMCLK
WS refers to the number of wait states inserted by hardware when using XREADY. If the zone is configured to ignore XREADY (USEREADY = 0),
then WS = 0.
Minimum wait state requirements must be met when configuring each zone’s XTIMING register. These
requirements are in addition to any timing requirements as specified by that device’s data sheet. No internal
device hardware is included to detect illegal settings.
If the XREADY signal is ignored (USEREADY = 0), then:
1.
Lead:
LR
≥
t
c(XTIM)
LW
≥
t
c(XTIM)
These requirements result in the following XTIMING register configuration restrictions
§
:
XRDLEAD
≥
1
§
No hardware to detect illegal XTIMING configurations
XRDACTIVE
≥
0
XRDTRAIL
≥
0
XWRLEAD
≥
1
XWRACTIVE
≥
0
XWRTRAIL
≥
0
X2TIMING
0, 1
Examples of valid and invalid timing when not sampling XREADY
§
:
XRDLEAD
0
1
XRDACTIVE
0
0
XRDTRAIL
0
0
XWRLEAD
0
1
XWRACTIVE
0
0
XWRTRAIL
0
0
X2TIMING
0, 1
0, 1
Invalid
Valid
§
No hardware to detect illegal XTIMING configurations
A
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