參數資料
型號: TMR320F2811GHHA
廠商: Texas Instruments, Inc.
元件分類: 數字信號處理
英文描述: TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述: TMS320R2811,TMS320R2812數字信號處理器
文件頁數: 113/147頁
文件大?。?/td> 2021K
代理商: TMR320F2811GHHA
Electrical Specifications
113
June 2004
SPRS257
If the XREADY signal is sampled in the Synchronous mode (USEREADY = 1, READYMODE = 0), then:
LR
t
c(XTIM)
LW
t
c(XTIM)
2.
Active:
AR
2 x t
c(XTIM)
AW
2 x t
c(XTIM)
NOTE
: Restriction does not include external hardware wait states
1.
Lead:
These requirements result in the following XTIMING register configuration restrictions
:
XRDLEAD
1
No hardware to detect illegal XTIMING configurations
XRDACTIVE
1
XRDTRAIL
0
XWRLEAD
1
XWRACTIVE
1
XWRTRAIL
0
X2TIMING
0, 1
Examples of valid and invalid timing when using Synchronous XREADY
:
XRDLEAD
0
1
1
XRDACTIVE
0
0
1
XRDTRAIL
0
0
0
XWRLEAD
0
1
1
XWRACTIVE
0
0
1
XWRTRAIL
0
0
0
X2TIMING
0, 1
0, 1
0, 1
Invalid
Invalid
Valid
No hardware to detect illegal XTIMING configurations
If the XREADY signal is sampled in the Asynchronous mode (USEREADY = 1, READYMODE = 1), then:
LR
t
c(XTIM)
LW
t
c(XTIM)
2.
Active:
AR
2 x t
c(XTIM)
AW
2 x t
c(XTIM)
NOTE
: Restriction does not include external hardware wait states
LR + AR
4 x t
c(XTIM)
LW + AW
4 x t
c(XTIM)
NOTE
: Restriction does not include external hardware wait states
1.
Lead:
3.
Lead + Active:
These requirements result in the following XTIMING register configuration restrictions
:
XRDLEAD
1
No hardware to detect illegal XTIMING configurations
or
XRDACTIVE
2
XRDTRAIL
0
XWRLEAD
1
XWRACTIVE
2
XWRTRAIL
0
X2TIMING
0, 1
XRDLEAD
2
No hardware to detect illegal XTIMING configurations
XRDACTIVE
1
XRDTRAIL
0
XWRLEAD
2
XWRACTIVE
1
XWRTRAIL
0
X2TIMING
0, 1
Examples of valid and invalid timing when using Asynchronous XREADY
:
XRDLEAD
0
1
1
1
1
2
XRDACTIVE
0
0
1
1
2
1
XRDTRAIL
0
0
0
0
0
0
XWRLEAD
0
1
1
1
1
2
XWRACTIVE
0
0
1
1
2
1
XWRTRAIL
0
0
0
0
0
0
X2TIMING
0, 1
0, 1
0
1
0, 1
0, 1
Invalid
Invalid
Invalid
Valid
Valid
Valid
No hardware to detect illegal XTIMING configurations
A
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