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參數(shù)資料
| 型號(hào)： | TMPR4955 |
| 廠商： | Toshiba Corporation |
| 英文描述： | 64-bit RISC (Reduced Instruction Set Computer) microprocessor(64位精簡(jiǎn)指令集系統(tǒng)計(jì)算機(jī)微處理器) |
| 中文描述： | 64位RISC（精簡(jiǎn)指令集計(jì)算機(jī)）微處理器（64位精簡(jiǎn)指令集系統(tǒng)計(jì)算機(jī)微處理器） |
| 文件頁數(shù)： | 19/60頁 |
| 文件大?。?/td> | 244K |
| 代理商： | TMPR4955 |
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TOSHIBA
TENTATIVE
TMPR4955/56
20-Oct.-1999
19
write requests when there are no read requests on hold.
When using processor input signals RdRdy* and WrRdy*, the external agent can control the processor
request flow. RdRdy* is the signal that controls the processor read flow, and WrRdy* controls the
processor write request flow. Figure 5-4 illustrates the sequence of the processor request cycle.
Figure 5-4 Processor Requests
5.5.3 Processor read requests
When the processor issues a read request, the external agent must access the specified resource and return
the requested data.
The external agent returns response data for processor read requests so they can be executed separately
from the requests. In other words, the external agent can start an external request before returning
response data for the processor read request. A processor read request is complete when the final word of
the response data is received from the external agent.
Depending on the data identifier combined with the response data, an error in the response data may be
pointed out. The processor would then treat this error as a bus error.
If data have not been returned to the issued processor read request, the applicable request is said to be “on
hold.” This state continues until the requested read data are returned.
The external agent must be able to accept processor read requests at any time if either of the two
following conditions is met.
There is no processor read request that is on hold.
The RdRdy* signal is asserted for 1 cycle 2 cycles before the issue cycle.
1.
Processor issues read/
write requests.
TX4956
External agent
2.
External
acceptance of requests by
asserting either RdRdy* or
WrRdy*.
system
controls
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