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參數(shù)資料
| 型號(hào)： | TMP320R2812GHHS |
| 廠商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | TMS320R2811, TMS320R2812 Digital Signal Processors |
| 中文描述： | TMS320R2811，TMS320R2812數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 97/147頁(yè) |
| 文件大?。?/td> | 2021K |
| 代理商： | TMP320R2812GHHS |
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Electrical Specifications
97
June 2004
SPRS257
6.15
Low-Power Mode Wakeup Timing
Table 6
9 is also the IDLE Mode Wake-Up Timing Requirements table.
Table 6
9. IDLE Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
Without input qualifier
With input qualifier
MIN
TYP
MAX
UNIT
Cycles
Cycles
t
w(WAKE-INT)
Pulse duration, external wake-up
signal
2 * t
c(SCO)
1 * t
c(SCO)
+ IQT
t
d(WAKE-IDLE)
Delay time, external wake signal to
program execution resume
Wake-up from SARAM
Wake-up from SARAM
Without input qualifier
With input qualifier
8 * t
c(SCO)
Cycles
Cycles
8 * t
c(SCO)
+ IQT
Input Qualification Time (IQT) = [5 x QUALPRD x 2] * t
c(SCO)
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the
wake-up) signal involves additional latency.
WAKE INT
XCLKOUT
A0
A15
t
d(WAKE
IDLE)
XCLKOUT = SYSCLKOUT
WAKE INT can be any enabled interrupt, WDINT, XNMI, or XRS.
t
w(WAKE
INT)
Figure 6
10. IDLE Entry and Exit Timing
Table 6
10 is also the STANDBY Mode Wake-Up Timing Requirements table.
Table 6
10. STANDBY Mode Switching Characteristics
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNIT
t
d(IDLE-XCOH)
Delay time, IDLE instruction
executed to XCLKOUT high
32 * t
c(SCO)
12 * t
c(CI)
Cycles
t
w(WAKE-INT)
Pulse duration, external
wake-up signal
Without input qualifier
With input qualifier
12 * t
c(CI)
Cycles
Cycles
(2 + QUALSTDBY)
* t
c(CI)
t
d(WAKE-STBY)
Delay time, external wake
signal to program execution
resume
Wake-up from SARAM
Wake-up from SARAM
Without input qualifier
With input qualifier
12 * t
c(CI)
Cycles
Cycles
12 * t
c(CI)
+ t
w(WAKE-INT)
QUALSTDBY is a 6-bit field in the LPMCR0 register.
This is the time taken to begin execution of the instruction that immediately follows the IDLE instruction. Execution of an ISR (triggered by the
wake-up) signal involves additional latency.
A
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