參數(shù)資料
型號： TMP320R2811GHHS
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述： TMS320R2811，TMS320R2812數(shù)字信號處理器
文件頁數(shù)： 141/147頁
文件大小： 2021K
代理商： TMP320R2811GHHS
Electrical Specifications
141
June 2004
SPRS257
Table 6
51. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 11b, CLKXP = 1)
NO.
MASTER
SLAVE
UNIT
MIN
P - 10
P - 10
MAX
MIN
MAX
M58
M59
t
su(DRV-CKXL)
t
h(CKXL-DRV)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
8P - 10
8P - 10
ns
ns
M60
t
su(FXL-CKXL)
Setup time, FSX low before CLKX low
16P +
10
ns
M61
t
c(CKX)
Cycle time, CLKX
2P
16P
ns
Table 6
52. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 11b, CLKXP = 1)
NO.
PARAMETER
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
M53
M54
t
h(CKXH-FXL)
t
d(FXL-CKXL)
Hold time, FSX low after CLKX high
Delay time, FSX low to CLKX low
Disable time, DX high impedance following last data bit
from CLKX high
P
ns
ns
2P
M56
t
dis(CKXH-DXHZ)
P+6
7P + 6
ns
M57
t
d(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
C =
CLKX low pulse width = P
D =
CLKX high pulse width = P
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
CLKX
FSX
DX
DR
M54
M58
M56
M53
M55
M59
M57
LSB
MSB
M60
M61
Figure 6
43. McBSP Timing as SPI Master or Slave: CLKSTP = 11b, CLKXP = 1
A
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