參數(shù)資料
型號(hào)： TMP320R2811GHHQ
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述： TMS320R2811，TMS320R2812數(shù)字信號(hào)處理器
文件頁數(shù)： 138/147頁
文件大?。?/td> 2021K
代理商： TMP320R2811GHHQ
Electrical Specifications
138
June 2004
SPRS257
6.30.2
McBSP as SPI Master or Slave Timing
Table 6
45. McBSP as SPI Master or Slave Timing Requirements (CLKSTP = 10b, CLKXP = 0)
NO.
MASTER
SLAVE
UNIT
MIN
P-10
P-10
MAX
MIN
8P-10
8P-10
MAX
M30
M31
t
su(DRV-CKXL)
t
h(CKXL-DRV)
t
su(BFXL-CKXH)
t
c(CKX)
Setup time, DR valid before CLKX low
Hold time, DR valid after CLKX low
ns
ns
M32
Setup time, FSX low before CLKX high
8P+10
ns
M33
Cycle time, CLKX
2P
16P
ns
Table 6
46. McBSP as SPI Master or Slave Switching Characteristics (CLKSTP = 10b, CLKXP = 0)
NO.
PARAMETER
MASTER
SLAVE
UNIT
MIN
MAX
MIN
MAX
M24
M25
t
h(CKXL-FXL)
t
d(FXL-CKXH)
Hold time, FSX low after CLKX low
Delay time, FSX low to CLKX high
Disable time, DX high impedance following
last data bit from FSX high
2P
P
ns
ns
M28
t
dis(FXH-DXHZ)
6
6P + 6
ns
M29
t
d(FXL-DXV)
Delay time, FSX low to DX valid
6
4P + 6
ns
2P = 1/CLKG
For all SPI slave modes, CLKX has to be minimum 8 CLKG cycles. Also CLKG should be LSPCLK/2 by setting CLKSM = CLKGDV = 1. With
maximum LSPCLK speed of 75 MHz, CLKX maximum frequency will be LSPCLK/16 , that is 4.5 MHz and P =13.3 ns.
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
Bit 0
Bit(n-1)
(n-2)
(n-3)
(n-4)
CLKX
FSX
DX
M30
M31
DR
M28
M24
M29
M25
LSB
MSB
M32
M33
Figure 6
40. McBSP Timing as SPI Master or Slave: CLKSTP = 10b, CLKXP = 0
A
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