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參數(shù)資料
| 型號： | TMP320LF2407APGA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DSP CONTROLLERS |
| 中文描述： | DSP控制器 |
| 文件頁數(shù)： | 16/134頁 |
| 文件大?。?/td> | 1759K |
| 代理商： | TMP320LF2407APGA |
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TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
DSP CONTROLLERS
SPRS145K
JULY 2000
REVISED AUGUST 2005
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
pin functions (continued)
Table 2. LF240xA and LC240xA Pin List and Package Options
(Continued)
PIN NAME
LF2407A
(144-PGE)
2406A
(100-PZ)
LC2404A
(100-PZ)
2403A,
LC2402A
(64-PAG)
and
2402A
(64-PG)
DESCRIPTION
EMULATION AND TEST (CONTINUED)
TDI
139
96
96
30
JTAG test data input (TDI) with internal pullup. TDI
is clocked into the selected register (instruction or
data) on a rising edge of TCK.
(
↑
)
TDO
142
99
99
31
JTAG scan out, test data output (TDO). The
contents of the selected register (instruction or
data) is shifted out of TDO on the falling edge of
TCK.
(
↓
)
JTAG test-mode select (TMS) with internal pullup.
This serial control input is clocked into the TAP
controller on the rising edge of TCK.
TMS
144
100
100
32
(
↑
)
TMS2
36
25
25
48
JTAG test-mode select 2 (TMS2) with internal
pullup. This serial control input is clocked into the
TAP controller on the rising edge of TCK. Used for
test and emulation only. This pin can be left
unconnected in user applications. If the PLL bypass
mode is desired, TMS2, TMS, and TRST should be
held low during reset.
(
↑
)
TRST
1
1
1
33
JTAG test reset with internal pulldown. TRST, when
driven high, gives the scan system control of the
operations of the device. If this signal is not
connected or driven low, the device operates in its
functional mode, and the test reset signals are
ignored.
(
↓
)
NOTE: Do not use pullup resistors on TRST; it has
an internal pulldown device. TRST is an active high
test pin and must be maintained low at all times
during normal device operation. In a low-noise
environment, TRST may be left floating. In other
instances, an external pulldown resistor is highly
recommended. The value of this resistor should be
based on drive strength of the debugger pods
applicable to the design. A 2.2-k
resistor generally
offers
adequate
protection.
application
specific, it is recommended that each
target board be validated for proper operation of the
debugger and the application. (I
↓
)
Since
this
is
Bold, italicized pin names
indicate pin function after reset.
GPIO
General-purpose input/output pin. All GPIOs come up as input after reset.
§
It is highly recommended that V
CCA
be isolated from the digital supply voltage (and V
SSA
from digital ground) to maintain the specified accuracy
and improve the noise immunity of the ADC.
Only when all of the following conditions are met: EMU1/OFF is low, TRST is low, and EMU0 is high
#
No power supply pin (V
DD
, V
DDO
, V
SS
, or V
SSO
) should be left unconnected. All power supply pins must be connected appropriately for proper
device operation.
LEGEND:
↑
Internal pullup
↓
Internal pulldown
(Typical active pullup/pulldown value is
±
16
μ
A.)
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相關(guān)代理商/技術(shù)參數(shù) |
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| TMP320LF2407APGEA | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|144PIN|PLASTIC |
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| TMP320LF2407APGS | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLERS |
| TMP320LF2407APZA | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLERS |
| TMP320LF2407APZS | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLERS |
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