
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145K
JULY 2000
REVISED AUGUST 2005
109
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
10-bit analog-to-digital converter (ADC) (continued)
internal ADC module timing
(see Figure 51)
MIN
MAX
UNIT
t
c(AD)
Cycle time, ADC prescaled clock
Pulse duration total sample/hold and
Pulse duration, total sample/hold and
conversion time
Delay time, start of conversion to beginning of sample and hold
l ti
l d l
33 3
33.3
ns
t
w(SHC)
500
ns
t
d(SOC-SH)
t
w(SH)
t
w(C)
t
d(EOC)
2t
c(CO)
2t
c(AD)§
10t
c(AD)
2t
c(CO)
ns
Pulse duration, sample and hold time
32t
c(AD)
ns
Pulse duration, total conversion time
ns
Delay time, end of conversion to data loaded into result register
ns
t
d(ADCINT)
The ADC timing diagram represents a typical conversion sequence. See the ADC chapter in the
TMS320LF/LC240xA DSP Controllers Reference
Guide: System and Peripherals
(literature number SPRU357) for more details.
The total sample/hold and conversion time is determined by the summation of t
d(SOC-SH)
, t
w(SH)
, t
w(C)
, and t
d(EOC)
.
§
Can be varied by ACQ Prescaler bits in the ADCTRL1 register
Delay time, ADC flag to ADC interrupt
2t
c(CO)
ns
0
3
2
4
5
1
t
w(C)
6
7
8
t
c(AD)
ADC Clock
Analog Input
Bit Converted
t
d(SOC
SH)
EOC/Convert
Internal Start/
Sample Hold
Start of Convert
XFR to RESULTn
t
w(SHC)
á
á
á
á
t
d(EOC)
9
t
w(SH)
t
d(ADCINT)
ADC Interrupt
Figure 51. Analog-to-Digital Internal Module Timing