參數(shù)資料
型號: TMP320LF2402AVFA
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: DSP CONTROLLERS
中文描述: DSP控制器
文件頁數(shù): 87/134頁
文件大小: 1759K
代理商: TMP320LF2402AVFA
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145K
JULY 2000
REVISED AUGUST 2005
87
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
TIMING EVENT MANAGER INTERFACE
PWM timing
PWM refers to all PWM outputs on EVA and EVB.
switching characteristics over recommended operating conditions for PWM timing
[H = 0.5t
c(CO)
] (see Figure 35)
PARAMETER
MIN
MAX
UNIT
t
w(PWM)
t
d(PWM)CO
PWM outputs may be 100%, 0%, or increments of t
c(CO)
with respect to the PWM period.
Pulse duration, PWMx output high/low
2H+5
ns
Delay time, CLKOUT low to PWMx output switching
15
ns
timing requirements
[H = 0.5t
c(CO)
] (see Figure 36)
MIN
MAX
UNIT
t
w(TMRDIR)
t
w(TMRCLK)
t
wh(TMRCLK)
t
c(TMRCLK)
Parameter TMRDIR is equal to the pin TDIRx, and parameter TMRCLK is equal to the pin TCLKINx.
Pulse duration, TMRDIR low/high
4H+5
ns
Pulse duration, TMRCLK low as a percentage of TMRCLK cycle time
40
60
%
Pulse duration, TMRCLK high as a percentage of TMRCLK cycle time
40
60
%
Cycle time, TMRCLK
4
t
c(CO)
ns
t
w(PWM)
t
d(PWM)CO
PWMx
CLKOUT
Figure 35. PWM Output Timing
CLKOUT
t
w(TMRDIR)
TMRDIR
Parameter TMRDIR is equal to the pin TDIRx.
Figure 36. TMRDIR Timing
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