參數(shù)資料
型號(hào)： TMP320LC2407AVFA
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DSP CONTROLLERS
中文描述： DSP控制器
文件頁數(shù)： 97/134頁
文件大小： 1759K
代理商： TMP320LC2407AVFA
TMS320LF2407A, TMS320LF2406A, TMS320LF2403A, TMS320LF2402A
TMS320LC2406A, TMS320LC2404A, TMS320LC2403A, TMS320LC2402A
DSP CONTROLLERS
SPRS145K
JULY 2000
REVISED AUGUST 2005
97
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
SPI slave mode timing parameters (continued)
SPI slave mode external timing parameters (clock phase = 1)
(see Figure 44)
NO.
MIN
MAX
UNIT
12
t
c(SPC)S
t
w(SPCH)S
t
w(SPCL)S
t
w(SPCL)S
t
w(SPCH)S
t
su(SOMI-SPCH)S
t
su(SOMI-SPCL)S
Cycle time, SPICLK
8t
c(CO)
0.5t
c(SPC)S
10
0.5t
c(SPC)S
10
0.5t
c(SPC)S
10
0.5t
c(SPC)S
10
0.125t
c(SPC)S
0.125t
c(SPC)S
ns
13
§
Pulse duration, SPICLK high (clock polarity = 0)
0.5t
c(SPC)S
0.5t
c(SPC)S
0.5t
c(SPC)S
0.5t
c(SPC)S
ns
Pulse duration, SPICLK low (clock polarity = 1)
14
§
Pulse duration, SPICLK low (clock polarity = 0)
ns
Pulse duration, SPICLK high (clock polarity = 1)
17
§
Setup time, SPISOMI before SPICLK high (clock polarity = 0)
ns
Setup time, SPISOMI before SPICLK low (clock polarity = 1)
18
§
t
v(SPCH-SOMI)S
Valid time, SPISOMI data valid after SPICLK high
(clock polarity =0)
0.75t
c(SPC)S
ns
t
v(SPCL-SOMI)S
Valid time, SPISOMI data valid after SPICLK low
(clock polarity =1)
0.75t
c(SPC)S
21
§
t
su(SIMO-SPCH)S
t
su(SIMO-SPCL)S
Setup time, SPISIMO before SPICLK high (clock polarity = 0)
0
ns
Setup time, SPISIMO before SPICLK low (clock polarity = 1)
0
22
§
t
v(SPCH-SIMO)S
Valid time, SPISIMO data valid after SPICLK high
(clock polarity = 0)
0.5t
c(SPC)S
ns
t
v(SPCL-SIMO)S
Valid time, SPISIMO data valid after SPICLK low
(clock polarity = 1)
0.5t
c(SPC)S
The MASTER/SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is set.
t
c
= system clock cycle time = 1/CLKOUT =
t
c(CO)
§
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
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