<pre id="8ll4c"><span id="8ll4c"></span></pre>
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    參數(shù)資料
    型號： TMP320LC2406APAGS
    廠商： Texas Instruments, Inc.
    元件分類： 數(shù)字信號處理
    英文描述： DSP CONTROLLERS
    中文描述： DSP控制器
    文件頁數(shù)： 55/134頁
    文件大?。?/td> 1759K
    代理商： TMP320LC2406APAGS
    TMS320LF2407A,TMS320LF2406A,TMS320LF2403A,TMS320LF2402A
    TMS320LC2406A,TMS320LC2404A,TMS320LC2403A,TMS320LC2402A
    DSP CONTROLLERS
    SPRS145K
    JULY 2000
    REVISED AUGUST 2005
    55
    POST OFFICE BOX 1443
    HOUSTON, TEXAS 77251
    1443
    serial peripheral interface (SPI) module
    Some 240xA devices include the four-pin serial peripheral interface (SPI) module. The SPI is a high-speed,
    synchronous serial I/O port that allows a serial bit stream of programmed length (one to sixteen bits) to be shifted
    into and out of the device at a programmable bit-transfer rate. Normally, the SPI is used for communications
    between the DSP controller and external peripherals or another processor. Typical applications include external
    I/O or peripheral expansion through devices such as shift registers, display drivers, and ADCs. Multidevice
    communications are supported by the master/slave operation of the SPI.
    The SPI module features include:
    Four external pins:
    SPISOMI: SPI slave-output/master-input pin
    SPISIMO: SPI slave-input/master-output pin
    SPISTE: SPI slave transmit-enable pin
    SPICLK: SPI serial-clock pin
    NOTE: All four pins can be used as GPIO, if the SPI module is not used.
    Two operational modes: master and slave
    Baud rate: 125 different programmable rates/10 Mbps at 40-MHz CPUCLK
    Data word length: one to sixteen data bits
    Four clocking schemes (controlled by clock polarity and clock phase bits) include:
    Falling edge without phase delay: SPICLK active high. SPI transmits data on the falling edge of the
    SPICLK signal and receives data on the rising edge of the SPICLK signal.
    Falling edge with phase delay: SPICLK active high. SPI transmits data one half-cycle ahead of the
    falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.
    Rising edge without phase delay: SPICLK inactive low. SPI transmits data on the rising edge of the
    SPICLK signal and receives data on the falling edge of the SPICLK signal.
    Rising edge with phase delay: SPICLK inactive low. SPI transmits data one half-cycle ahead of the
    falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.
    Simultaneous receive and transmit operation (transmit function can be disabled in software)
    Transmitter and receiver operations are accomplished through either interrupt-driven or polled algorithms.
    Nine SPI module control registers: Located in control register frame beginning at address 7040h.
    NOTE: All registers in this module are 16-bit registers that are connected to the 16-bit peripheral bus. When a register is accessed, the
    register data is in the lower byte (7
    0), and the upper byte (15
    8) is read as zeros. Writing to the upper byte has no effect.
    相關(guān)PDF資料
    PDF描述
    TMP320LC2406APGA DSP CONTROLLERS
    TMP320LC2406APGEA DSP CONTROLLERS
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    TMP320LC2406APGS DSP CONTROLLERS
    TMP320LC2406AVFA DSP CONTROLLERS
    相關(guān)代理商/技術(shù)參數(shù)
    參數(shù)描述
    TMP320LC2406APGA 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLERS
    TMP320LC2406APGEA 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLERS
    TMP320LC2406APGES 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLERS
    TMP320LC2406APGS 制造商:TI 制造商全稱:Texas Instruments 功能描述:DSP CONTROLLERS
    TMP320LC2406APZA 制造商:未知廠家 制造商全稱:未知廠家 功能描述:DSP|16-BIT|CMOS|QFP|100PIN|PLASTIC
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