
Peripherals
72
 June 2004
SPRS257
Figure 4
10 shows the SCI module block diagram.
TX FIFO _0
LSPCLK
WUT
Frame Format and Mode
Even/Odd
SCICCR.6   SCICCR.5
Enable
Parity
SCI RX Interrupt select logic
BRKDT
SCIRXST.5
RXRDY
SCIRXST.6
SCICTL1.3
1
8
SCICTL2.1
RX/BK INT ENA
SCIRXD
SCIRXST.1
TXENA
SCI TX Interrupt select logic
TX EMPTY
SCICTL2.6
TXRDY
SCICTL2.7
SCICTL2.0
TX INT ENA
SCITXD
RXENA
SCICTL1.0
SCIRXD
RXWAKE
SCICTL1.6
RX ERR INT ENA
TXWAKE
SCITXD
SCITXBUF.7
0
SCIHBAUD. 15 
 8
Baud Rate
MSbyte
Register
SCILBAUD. 7 
 0
 Transmitter
Data
Buffer Register
8
Baud Rate
LSbyte
Register
 RXSHF
Register
 TXSHF
Register
8
TX FIFO registers
TX FIFO 
TX Interrupt
Logic
TXINT
SCIFFTX.14
RX FIFO _0
SCIRXBUF.7
0
Receive Data
Buffer register
SCIRXBUF.7
0
8
RX FIFO registers
RX Interrupt
Logic
RXINT
RX FIFO 
SCIFFRX.15
RXFFOVF
RX Error
SCIRXST.7
RX Error
PE
FE OE
SCIRXST.4 
 2
To CPU
To CPU
AutoBaud Detect logic
SCICTL1.1
SCIFFENA
Figure 4
10. Serial Communications Interface (SCI) Module Block Diagram
A