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參數(shù)資料
| 型號(hào)： | TMP320F2810PGFAEP |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | Digital Signal Processors |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 16/103頁 |
| 文件大?。?/td> | 1341K |
| 代理商： | TMP320F2810PGFAEP |
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TMS320F2810, TMS320F2812
DIGITAL SIGNAL PROCESSORS
SPRS174B
–
APRIL 2001
–
REVISED SEPTEMBER 2001
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
–
1443
description
The TMS320F2810 and TMS320F2812 devices, members of the TMS320C28x
DSP generation, are highly
integrated, high-performance solutions for demanding control applications. The functional blocks and the
memory maps are described in subsequent paragraphs.
C28x CPU
The C28x
DSP generation is the newest member of the TMS320C2000
DSP platform. The C28x is source
code compatible to the 24x/240x DSP devices, hence existing 240x users can leverage their significant software
investment. Additionally, the C28x is a very efficient C/C++ engine, hence enabling users to develop not only
their system control software in a high-level language, but also enables math algorithms to be developed using
C/C++. The C28x is as efficient in DSP math tasks as it is in system control tasks that typically are handled by
microcontroller devices. This efficiency removes the need for a second processor in many systems. The 32 x
32-bit MAC capabilities of the C28x and its 64-bit processing capabilities, enable the C28x to efficiently handle
higher numerical resolution problems that would otherwise demand a more expensive floating-point processor
solution. Add to this the fast interrupt response with automatic context save of critical registers, resulting in a
device that is capable of servicing many asynchronous events with minimal latency. The C28x has an
8-level-deep protected pipeline with pipelined memory accesses. This pipelining enables the C28x to execute
at high speeds without resorting to expensive high-speed memories. Special branch-look-ahead hardware
minimizes the latency for conditional discontinuities. Special store conditional operations further improve
performance.
memory bus (Harvard bus architecture)
As with many DSP type devices, multiple busses are used to move data between the memories and peripherals
and the CPU. The C28x memory bus architecture contains a program read bus, data read bus and data write
bus. The program read bus consists of 22 address lines and 32 data lines. The data read and write busses
consist of 32 address lines and 32 data lines each. The 32-bit-wide data busses enable single cycle 32-bit
operations. The multiple bus architecture, commonly termed
“
Harvard Bus
”
, enables the C28x to fetch an
instruction, read a data value and write a data value in a single cycle. All peripherals and memories attached
to the memory bus will prioritize memory accesses. Generally, the priority of Memory Bus accesses can be
summarized as follows:
Data Writes
Program Writes
Highest:
Data Reads
Program Reads
Fetches
Lowest:
peripheral bus
To enable migration of peripherals between various Texas Instruments (TI) DSP family of devices, the F2810
and F2812 adopt a peripheral bus standard for peripheral interconnect. The peripheral bus bridge multiplexes
the various busses that make up the processor
“
Memory Bus
”
into a single bus consisting of 16 address lines
and 16 or 32 data lines and associated control signals. There are two versions of the peripheral bus supported
on the F2810 and F2812. One version only supports 16-bit accesses (called peripheral frame 2) and this retains
compatibility with C240x compatible peripherals. The other version supports both 16- and 32-bit accesses
(called peripheral frame 1) and is used to connect peripherals requiring higher throughput.
P
TMS320C28x, C28x, and TMS320C2000 are trademarks of Texas Instruments.
Simultaneous Data and Program writes cannot occur on the Memory Bus.
Simultaneous Program Reads and Fetches cannot occur on the Memory Bus.
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