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    參數(shù)資料
    

    


    


    
型號：
TMP320F2810GHHS

    

    
廠商：
Texas Instruments, Inc.

    

    
元件分類：
數(shù)字信號處理

    

    
英文描述：
DIGITAL SIGNAL PROCESSORS

    

    
中文描述：
數(shù)字信號處理器

    

    
文件頁數(shù)：
62/103頁

    

    
文件大小：
1341K

    

    
代理商：
TMP320F2810GHHS


    

    

    

	
    
    
    

    
    
	
    TMS320F2810, TMS320F2812
    DIGITAL SIGNAL PROCESSORS
    SPRS174B 
    –
     APRIL 2001 
    –
     REVISED SEPTEMBER 2001
    62
    POST OFFICE BOX 1443 
     HOUSTON, TEXAS 77251
    –
    1443
    event manager modules (EVA, EVB) (continued)
    Table 52. EV-A Registers
    NAME
    ADDRESS RANGE
    SIZE
    (x16)
    DESCRIPTION
    GPTCONA
    0x0000
    –
    7400
    1
    GP Timer Control Register A
    T1CNT
    0x0000
    –
    7401
    1
    GP Timer 1 Counter Register
    T1CMPR
    0x0000
    –
    7402
    1
    GP Timer 1 Compare Register
    T1PR
    0x0000
    –
    7403
    1
    GP Timer 1 Period Register
    T1CON
    0x0000
    –
    7404
    1
    GP Timer 1 Control Register
    T2CNT
    0x0000
    –
    7405
    1
    GP Timer 2 Counter Register
    T2CMPR
    0x0000
    –
    7406
    1
    GP Timer 2 Compare Register
    T2PR
    0x0000
    –
    7407
    1
    GP Timer 2 Period Register
    T2CON
    EXTCONA
    0x0000
    –
    7408
    1
    GP Timer 2 Control Register
    0x0000
    –
    7409
    1
    GP Extension Control Register A
    COMCONA
    0x0000
    –
    7411
    1
    Compare Control Register A
    ACTRA
    0x0000
    –
    7413
    1
    Compare Action Control Register A
    DBTCONA
    0x0000
    –
    7415
    1
    Dead-Band Timer Control Register A
    CMPR1
    0x0000
    –
    7417
    1
    Compare Register 1
    CMPR2
    0x0000
    –
    7418
    1
    Compare Register 2
    CMPR3
    0x0000
    –
    7419
    1
    Compare Register 3
    CAPCONA
    0x0000
    –
    7420
    1
    Capture Control Register A
    CAPFIFOA
    0x0000
    –
    7422
    1
    Capture FIFO Status Register A
    CAP1FIFO
    0x0000
    –
    7423
    1
    Two-Level Deep Capture FIFO Stack 1
    CAP2FIFO
    0x0000
    –
    7424
    1
    Two-Level Deep Capture FIFO Stack 2
    CAP3FIFO
    0x0000
    –
    7425
    1
    Two-Level Deep Capture FIFO Stack 3
    CAP1FBOT
    0x0000
    –
    7427
    1
    Bottom Register Of Capture FIFO Stack 1
    CAP2FBOT
    0x0000
    –
    7428
    1
    Bottom Register Of Capture FIFO Stack 2
    CAP2FBOT
    0x0000
    –
    7429
    1
    Bottom Register Of Capture FIFO Stack 3
    EVAIMRA
    0x0000
    –
    742C
    1
    Interrupt Mask Register A
    EVAIMRB
    0x0000
    –
    742D
    1
    Interrupt Mask Register B
    EVAIMRC
    0x0000
    –
    742E
    1
    Interrupt Mask Register C
    EVAIFRA
    0x0000
    –
    742F
    1
    Interrupt Flag Register A
    EVAIFRB
    0x0000
    –
    7430
    1
    Interrupt Flag Register B
    EVAIFRC
    0x0000
    –
    7431
    1
    Interrupt Flag Register C
    The EV-B register set is identical except the address range is from 0x0000
    –
    7500 to 0x0000
    –
    753F. The above registers are mapped to Zone 2.
    This space allows only 16-bit accesses. 32-bit accesses produce undefined results.
    New register compared to 24x/240x
    P
    
    
    
    
    
    


    


    

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