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| 型號(hào)： | TMP320C6413GTSA400 |
| 廠(chǎng)商： | Texas Instruments, Inc. |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理 |
| 英文描述： | Fixed-Point Digital Signal Processors |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 52/140頁(yè) |
| 文件大小： | 1958K |
| 代理商： | TMP320C6413GTSA400 |
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Device Configurations
52
April 2004
Revised May 2005
SPRS247E
3.7
Multiplexed Pins
Multiplexed pins are pins that are shared by more than one peripheral and are internally multiplexed. Some
of these pins are configured by software, and the others are configured by external pullup/pulldown resistors
only at reset. Those muxed pins that are configured by software should
not
be programmed to switch
functionalities during run-time. Those muxed pins that are configured by external pullup/pulldown resistors
are mutually exclusive; only one peripheral has primary control of the function of these pins after reset.
Table 3
8 identifies the multiplexed pins on the C6413/C6410 device; shows the default (primary) function and
the default settings after reset; and describes the pins, registers, etc. necessary to configure specific
multiplexed functions.
Table 3
8. C6413/C6410 Device Multiplexed Pins
MULTIPLEXED PINS
NAME
IPD/IPU
DEFAULT
FUNCTION
DEFAULT
SETTING
DESCRIPTION
NO.
CLKOUT4/GP0[1]
A2
IPU
CLKOUT4
GP1EN = 0 (disabled)
These pins are software-configurable. To use
these pins as GPIO pins, the GPxEN bits in the
GPIO Enable Register and the GPxDIR bits in
the GPIO Direction Register must be properly
configured.
GPxEN = 1:
GPx pin enabled
GPxDIR = 0:
GPx pin is an input
GPxDIR = 1:
GPx pin is an output
CLKOUT6/GP0[2]
B3
IPU
CLKOUT6
GP2EN = 0 (disabled)
HCNTL0/AFSR1[1]
HHWIL/AFSR1[2]
HR/W/AFSR1[3]
HAS/ACLKR1[1]
HCS/ACLKR1[2]
HDS1/ACLKR1[3]
HD29/AMUTEIN1
HD28/AMUTE1
HD27/AHCLKX1
HD26/AHCLKR1
HD25/ACLKR1
HD24/ACLKX1
HD23/AFSR1
HD22/AFSX1
Y6
Y7
AA5
Y5
AA11
AB11
W11
W10
Y4
AB4
AA9
AA4
AB9
AB5
B d f
By default, HPI32 is enabled upon reset
(McASP1 is disabled)
(McASP1 is disabled).
To enable the
McASP1
peripheral, the
TOUT0/
HPI_EN
pin must be
high
at reset either
i
via an external pullup (PU) resistor (1 k
) or
driven by a control device (disabling the HPI).
lt HPI32 i
bl d
i t (1 k
HPI pin
function
= 0
TOUT0/
HPI_EN
0
,
HD5 = 1
32 Bit HPI enabled)
(
32-Bit HPI enabled)
IPU
or
the McASP1 peripheral pins can be used if the
HPI is used as a 16 bit width [HPI EN 0
HPI is used as a 16-bit width [HPI_EN = 0,
HD5 =
0].
HHWIL pin
(HPI16 only)
McASP1 pins disabled.
The clocks and frame syncs select bits
(AFCMUX[1:0]) located in the PERCFG register
determine which of the clock and frame sync
pairs are input to McASP1. For more detailed
pa s a e
c S
information, see the Device Configuration
section of this data sheet.
o e de a ed
HD21/AXR1[5]
Y9
By default, HPI32 is enabled upon reset
(McASP1 is disabled).
To enable the
McASP1
peripheral, the
TOUT0/
HPI_EN
pin must be
high
at reset either
via an external pullup (PU) resistor (1 k
) or
driven by a control device (disabling the HPI).
HD20/AXR1[4]
AB8
HD19/AXR1[3]
AA6
IPU
HPI pin
function
TOUT0/
HPI_EN
= 0
,
HD5 = 1
32 Bit HPI enabled)
(
32-Bit HPI enabled)
HD18/AXR1[2]
AB7
McASP1 pins disabled.
or
the McASP1 peripheral pins can be used if the
HPI is used as a 16-bit width [HPI_EN = 0,
HD5
HD5 =
0].
HD17/AXR1[1]
AA7
McASP1 pin direction is controlled by the
PDIR[x] bits in the McASP1PDIR register.
McASP1PDIR = 0 input, = 1 output
HD16/AXR1[0]
AB6
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