TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
19
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
signal groups description (continued)
CE3
CE2
CE1
CE0
ECLKOUT
ARE/SDCAS/SSADS
ED[31:0]
EA[21:2]
BE3
BE2
BE1
BE0
TOUT1
TINP1
CLKX1
FSX1
DX1
CLKR1
FSR1
DR1
CLKS1
AOE/SDRAS/SSOE
AWE/SDWE/SSWE
ARDY
TOUT0
TINP0
CLKX0
FSX0
DX0
CLKR0
FSR0
DR0
CLKS0
Data
Memory Map
Space Select
Address
Byte Enables
32
20
Memory
Control
EMIF
(External Memory Interface)
Timer 1
Receive
Receive
Timer 0
Timers
McBSP1
McBSP0
Transmit
Transmit
Clock
Clock
McBSPs
(Multichannel Buffered Serial Ports)
ECLKIN
HOLD
HOLDA
BUSREQ
Bus
Arbitration
Figure 3. Peripheral Signals