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參數(shù)資料
| 型號(hào)： | TMP320C6202BGLZ167 |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | FIXED-POINT DIGITAL SIGNAL PROCESSORS |
| 中文描述： | 定點(diǎn)數(shù)字信號(hào)處理器 |
| 文件頁(yè)數(shù)： | 42/83頁(yè) |
| 文件大?。?/td> | 1176K |
| 代理商： | TMP320C6202BGLZ167 |
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TMS320C6211, TMS320C6211B
FIXED-POINT DIGITAL SIGNAL PROCESSORS
SPRS073K
AUGUST 1998
REVISED MARCH 2004
42
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251
1443
PARAMETER MEASUREMENT INFORMATION (CONTINUED)
timing parameters and board routing analysis
The timing parameter values specified in this data sheet do
not
include delays by board routings. As a good
board design practice, such delays must
always
be taken into account. Timing values may be adjusted by
increasing/decreasing such delays. TI recommends utilizing the available I/O buffer information specification
(IBIS) models to analyze the timing characteristics correctly. If needed, external logic hardware such as buffers
may be used to compensate any timing differences. For example:
In typical boards with the C6211B commercial temperature device, the routing delay improves the external
memory’s ability to meet the DSP’s EMIF data input hold time requirement [t
h(EKOH-EDV)
].
In some boards with the C6211BGFNA extended temperature device, the routing delay improves the
external memory’s ability to meet the DSP’s EMIF data input hold time requirement [t
h(EKOH-EDV)
]. In
addition, it may be necessary to add an extra delay to the input clock of the external memory to robustly
meet the DSP’s data input hold time requirement. If the extra delay approach is used, memory bus
frequency adjustments may be needed to ensure the DPS’s input setup time requirement [t
su(EDV-EKOH)
]
is still maintained.
For inputs, timing is most impacted by the round-trip propagation delay from the DSP to the external device and
from the external device to the DSP. This round-trip delay tends to negatively impact the input setup time margin,
but also tends to improve the input hold time margins (see Table 21 and Figure 12).
Figure 12 represents a general transfer between the DSP and an external device. The figure also represents
board route delays and how they are perceived by the DSP and the external device.
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