• 參數(shù)資料
    型號: TMP320C6202BGDP167
    廠商: Texas Instruments, Inc.
    元件分類: 數(shù)字信號處理
    英文描述: FIXED-POINT DIGITAL SIGNAL PROCESSORS
    中文描述: 定點數(shù)字信號處理器
    文件頁數(shù): 2/83頁
    文件大?。?/td> 1176K
    代理商: TMP320C6202BGDP167
    TMS320C6211, TMS320C6211B
    FIXED-POINT DIGITAL SIGNAL PROCESSORS
    SPRS073K
    AUGUST 1998
    REVISED MARCH 2004
    2
    POST OFFICE BOX 1443
    HOUSTON, TEXAS 77251
    1443
    Table of Contents
    absolute maximum ratings over operating case
    temperature range
    recommended operating conditions
    electrical characteristics over recommended ranges of
    supply voltage and operating case temperature
    parameter measurement information
    signal transition levels
    . . . . . . . . . . . . . . . . . . . . . . . . . .
    timing parameters and board routing analysis
    input and output clocks
    . . . . . . . . . . . . . . . . . . . . . . . . . . .
    asynchronous memory timing
    synchronous-burst memory timing
    synchronous DRAM timing
    . . . . . . . . . . . . . . . . . . . . . . . .
    HOLD/HOLDA timing
    . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    BUSREQ timing
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    reset timing
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    external interrupt timing
    . . . . . . . . . . . . . . . . . . . . . . . . . .
    host-port interface timing
    . . . . . . . . . . . . . . . . . . . . . . . . .
    multichannel buffered serial port timing
    timer timing
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    JTAG test-port timing
    . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    mechanical data
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    revision history
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    40
    40
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    40
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    47
    50
    52
    58
    59
    60
    62
    63
    67
    78
    79
    80
    81
    .
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    . . . . . . . . . . . . . . . . .
    . . . . . . . . . . . . .
    GFN BGA package (bottom view)
    description
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    device characteristics
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    device compatibility
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    functional block and CPU (DSP core) diagram
    CPU (DSP core) description
    . . . . . . . . . . . . . . . . . . . . . . . . . .
    memory map summary
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    peripheral register descriptions
    PWRD bits in CPU CSR register description
    EDMA channel synchronization events
    interrupt sources and interrupt selector
    signal groups description
    . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    terminal functions
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    development support
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    documentation support
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    clock PLL
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    power-down logic
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    power-supply sequencing
    . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    IEEE 1149.1 JTAG compatibility statement
    EMIF device speed
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    bootmode
    . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
    2
    3
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    9
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    10
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    39
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    . . . . . . . . . . . . . . . .
    . . . . . . . . . . . . . . . .
    . . . . . . . . . . . . .
    GFN BGA package (bottom view)
    19
    15
    17
    13
    11
    9
    Y
    W
    V
    U
    T
    R
    P
    N
    M
    7
    5
    L
    K
    J
    H
    G
    F
    E
    3
    1
    D
    C
    B
    A
    2
    4
    6
    8
    20
    18
    16
    14
    12
    10
    GFN 256-PIN BALL GRID ARRAY (BGA) PACKAGE
    (BOTTOM VIEW)
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