參數(shù)資料
型號： TMP320C2812GHHA
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述： TMS320R2811，TMS320R2812數(shù)字信號處理器
文件頁數(shù)： 92/147頁
文件大小： 2021K
代理商： TMP320C2812GHHA
Electrical Specifications
92
June 2004
SPRS257
6.13.2
Output Clock Characteristics
Table 6
7. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)
No.
PARAMETER
MIN
6.67
§
TYP
MAX
UNIT
C1
C3
C4
C5
C6
t
c(XCO)
t
f(XCO)
t
r(XCO)
t
w(XCOL)
t
w(XCOH)
t
p
Cycle time, XCLKOUT
Fall time, XCLKOUT
Rise time, XCLKOUT
Pulse duration, XCLKOUT low
Pulse duration, XCLKOUT high
ns
ns
ns
ns
ns
2
2
H
2
H
2
H+2
H+2
C7
PLL lock time
131072t
c(CI)
ns
A load of 40 pF is assumed for these parameters.
H = 0.5t
c(XCO)
§
The PLL must be used for maximum frequency operation.
C4
C3
XCLKOUT
(see Note B)
XCLKIN
C5
C9
C10
C1
C8
C6
(see Note A)
NOTES: A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in Figure 6
5 is
intended to illustrate the timing parameters only and may differ based on configuration.
B. XCLKOUT configured to reflect SYSCLKOUT.
Figure 6
5. Clock Timing
6.14
Reset Timing
Table 6
8. Reset (XRS) Timing Requirements
MIN
NOM
MAX
UNIT
t
w(RSL1)
Pulse duration, stable XCLKIN to XRS high
8t
c(CI)
cycles
t
w(RSL2)
Pulse duration XRS low
Pulse duration, XRS low
Warm reset
8t
c(CI)
cycles
WD-initiated reset
512t
c(CI)
512t
c(CI)
32t
c(CI)
t
w(WDRS)
t
d(EX)
t
OSCST
Pulse duration, reset pulse generated by watchdog
cycles
Delay time, address/data valid after XRS high
cycles
Oscillator start-up time
1
10
ms
t
su(XPLLDIS)
Setup time for XPLLDIS pin
16t
c(CI)
cycles
t
h(XPLLDIS)
Hold time for XPLLDIS pin
16t
c(CI)
cycles
t
h(XMP/MC)
Hold time for XMP/MC pin
16t
c(CI)
2520t
c(CI)§
cycles
t
h(boot-mode)
If external oscillator/clock source are used, reset time has to be low at least for 1 ms after V
DD
reaches 1.5 V.
Dependent on crystal/resonator and board design.
Hold time for boot-mode pins
cycles
A
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