參數資料
型號： TMP320C2811GHHA
廠商： Texas Instruments, Inc.
元件分類： 數字信號處理
英文描述： TMS320R2811, TMS320R2812 Digital Signal Processors
中文描述： TMS320R2811，TMS320R2812數字信號處理器
文件頁數： 105/147頁
文件大?。?/td> 2021K
代理商： TMP320C2811GHHA
E
1
S
6.19
SPI Master Mode Timing
Table 6
20. SPI Master Mode External Timing (Clock Phase = 0)
NO.
SPI WHEN (SPIBRR + 1) IS EVEN
OR SPIBRR = 0 OR 2
SPI WHEN (SPIBRR + 1)
IS ODD AND SPIBRR > 3
UNIT
MIN
MAX
MIN
MAX
1
t
c(SPC)M
Cycle time, SPICLK
Pulse duration, SPICLK high
(clock polarity = 0)
4t
c(LCO)
128t
c(LCO)
5t
c(LCO)
127t
c(LCO)
ns
2
§
t
w(SPCH)M
0.5t
c(SPC)M
10
0.5t
c(SPC)M
0.5t
c(SPC)M
0.5t
c(LCO)
10
0.5t
c(SPC)M
0.5t
c(LCO)
ns
t
w(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 1)
0.5t
c(SPC)M
10
0.5t
c(SPC)M
0.5t
c(SPC)M
0.5t
c(LCO)
10
0.5t
c(SPC)M
0.5t
c(LCO)
3
§
t
w(SPCL)M
Pulse duration, SPICLK low
(clock polarity = 0)
0.5t
c(SPC)M
10
0.5t
c(SPC)M
0.5t
c(SPC)M
+0.5t
c(LCO)
10
0.5t
c(SPC)M
+ 0.5t
c(LCO)
ns
t
w(SPCH)M
Pulse duration, SPICLK high
(clock polarity = 1)
0.5t
c(SPC)M
10
0.5t
c(SPC)M
0.5t
c(SPC)M
+0.5t
c(LCO)
10
0.5t
c(SPC)M
+ 0.5t
c(LCO)
4
§
t
d(SPCH-SIMO)M
Delay time, SPICLK high to
SPISIMO valid (clock polarity = 0)
10
10
10
10
ns
t
d(SPCL-SIMO)M
Delay time, SPICLK low to
SPISIMO valid (clock polarity = 1)
10
10
10
10
5
§
t
v(SPCL-SIMO)M
Valid time, SPISIMO data valid
after SPICLK low
(clock polarity = 0)
0.5t
c(SPC)M
10
0.5t
c(SPC)M
+0.5t
c(LCO)
10
ns
t
v(SPCH-SIMO)M
Valid time, SPISIMO data valid
after SPICLK high
(clock polarity = 1)
0.5t
c(SPC)M
10
0.5t
c(SPC)M
+0.5t
c(LCO)
10
8
§
t
su(SOMI-SPCL)M
Setup time, SPISOMI before
SPICLK low (clock polarity = 0)
0
0
ns
t
su(SOMI-SPCH)M
Setup time, SPISOMI before
SPICLK high (clock polarity = 1)
0
0
9
§
t
v(SPCL-SOMI)M
Valid time, SPISOMI data valid
after SPICLK low
(clock polarity = 0)
Valid time, SPISOMI data valid
after SPICLK high
(clock polarity = 1)
0.25t
c(SPC)M
10
0.5t
c(SPC)M
0.5t
c(LCO)
10
ns
t
v(SPCH-SOMI)M
0.25t
c(SPC)M
10
0.5t
c(SPC)M
0.5t
c(LCO)
10
The MASTER/SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.
t
c(SPC)
= SPI clock cycle time = LS4
(SPIBRR
t
c(LCO)
= LSPCLK cycle time
§
The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).
NOTE: Internal clock prescalers must be adjusted such that the SPI clock speed is not greater than the I/O buffer speed limit (20 MHz).
or
LSPCLK
1)
ADVANCE INFORMATION
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