參數(shù)資料
型號： TMDS361PAGR
廠商： TEXAS INSTRUMENTS INC
元件分類： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： PLASTIC, TQFP-64
文件頁數(shù)： 24/43頁
文件大?。?/td> 2159K
代理商： TMDS361PAGR
SINK
HDMIRX
DDC_SDA
DDC_SCL
5 V
47kW
3.3 V
4.7kW
CEC
4.02 k W 10%
E-EDID
mController
HPD1
SDA1
SCL1
HPD2
SDA2
SCL2
HPD3
SDA3
SCL3
EQ
S1
S2
HPD_SINK
SDA_SINK
SCL_SINK
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
VSADJ
GND
SDA SCL
CEC
LOGIC
CEC
PHY
1 kW
1 k W
HPD
5V
SDA
SCL
CEC
CLK
D0
D1
D2
HPD
5V
SDA
SCL
CEC
CLK
D0
D1
D2
HPD
5V
SDA
SCL
CEC
CLK
D0
D1
D2
HPD
5V
SDA
SCL
CEC
CLK
D0
D1
D2
HPD
5V
SDA
SCL
CEC
CLK
D0
D1
D2
HPD
5V
SDA
SCL
CEC
CLK
D0
D1
D2
SOURCE1
With ACCoupled
HDMIOutput
SOURCE2
WithDCCoupled
HDMIOutput
SOURCE3
inGeneral
HDMIOutput
A11/B11
A12/B12
A13/B13
A14/B14
A21/B21
A22/B22
A23/B23
A24/B24
A31/B31
A32/B32
A33/B33
A34/B34
VDD
(5V)
VCC
(3.3V)
Y1/Z1
Y2/Z2
Y3/Z3
Y4/Z4
I
2C INTERFACE NOTES
SLLS919A – DECEMBER 2008 – REVISED JANUARY 2009............................................................................................................................................ www.ti.com
Figure 35. Three-Port HDMI-Enabled DTV With TMDS361 – CEC Commands Active
The I2C interface is used to access the internal registers of the TMDS361. I2C is a two-wire serial interface
developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of
a data line (SDA) and a clock line (SCL) with pullup structures. When the bus is idle, both SDA and SCL lines
are pulled high. All the I2C-compatible devices connect to the I2C bus through open-drain I/O pins, SDA and
SCL. A master device, usually a microcontroller or a digital signal processor, controls the bus. The master is
responsible for generating the SCL signal and device addresses. The master also generates specific conditions
that indicate the START and STOP of data transfer. A slave device receives and/or transmits data on the bus
under control of the master device. The TMDS361 works as a slave and supports standard-mode transfer (100
kbps).
The basic I2C start and stop access cycles are shown in Figure 36.
The basic access cycle consists of the following:
A start condition
A slave address cycle
Any number of data cycles
A stop condition
30
Copyright 2008–2009, Texas Instruments Incorporated
Product Folder Link(s) :TMDS361
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