參數(shù)資料
型號(hào)： TMDS261BPAGR
廠(chǎng)商： TEXAS INSTRUMENTS INC
元件分類(lèi)： 消費(fèi)家電
英文描述： SPECIALTY CONSUMER CIRCUIT, PQFP64
封裝： GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 35/49頁(yè)
文件大?。?/td> 11321K
代理商： TMDS261BPAGR
EXAMPLE – READING FROM THE TMDS261B
TMDS261B Read Phase 1
TMDS261B Read Phase 2
SLLS987 – SEPTEMBER 2009 .......................................................................................................................................................................................... www.ti.com
Step 8
0
I2C stop (master)
P
An example of the proper bit control for selecting port 2 is:
Step 4: 0000 0001
Step 6: 1001 0000
The read operation consists of two phases. The first phase is the address phase. In this phase, an I2C master
initiates a write operation to the TMDS261B by generating a start condition (S) followed by the TMDS261B I2C
address, in MSB-first bit order, followed by a 0 to indicate a write cycle. After receiving acknowledges from the
TMDS261B, the master presents the subaddress of the register to be read. After the cycle is acknowledged (A),
the master may optionally terminate the cycle by generating a stop condition (P).
The second phase is the data phase. In this phase, an I2C master initiates a read operation to the TMDS261B by
generating a start condition followed by the TMDS261B I2C address (as shown following for a read operation), in
MSB first bit order, followed by a 1 to indicate a read cycle. After an acknowledge from the TMDS261B, the I2C
master receives one byte of data from the TMDS261B. The master can continue receiving data byes by issuing
an acknowledge after each byte read (steps 10, 11). After the last data byte has been transferred from the
TMDS261B to the master, the master generates a not-acknowledge followed by a stop.
Step 1
0
I2C start (master)
S
Step 2
7
6
5
4
3
2
1
0
I2C general address (master)
0
1
0
1
0
Step 3
8
I2C acknowledge (slave)
A
Step 4
7
6
5
4
3
2
1
0
I2C write sink logic address (master)
0
Addr
Where Addr is determined by the values shown in Table 7.
Step 5
8
I2C acknowledge (slave)
A
Step 6
0
I2C stop (master)
P
Step 6 is optional.
Step 7
0
I2C start (master)
S
Step 8
7
6
5
4
3
2
1
0
I2C general address (master)
0
1
0
1
0
1
Step 9
8
I2C acknowledge (slave)
A
40
Copyright 2009, Texas Instruments Incorporated
Product Folder Link(s) :TMDS261B
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