參數(shù)資料
型號: TMC2250AH5C2
廠商: FAIRCHILD SEMICONDUCTOR CORP
元件分類: 數(shù)字信號處理外設
英文描述: Matrix Multiplier 12 x 10 bit, 50 MHz
中文描述: 12-BIT, DSP-MULTIPLIER, PPGA120
封裝: PLASTIC, PGA-120
文件頁數(shù): 6/23頁
文件大?。?/td> 186K
代理商: TMC2250AH5C2
PRODUCT SPECIFICATION
TMC2250A
6
REV. 1.0.2 10/25/00
Pin Descriptions
Pin Name
Pin Number
Function
Pin Description
CPGA/PPGA/
MPGA
MQFP
Power
V
DD
F3, H3, L7, C8,
C4
E3, G3, J3, L4,
L6, H11, C7,
C5
12, 20, 46,
102, 118
8, 16, 24, 34,
42, 72, 106,
114
Supply
Voltage
Ground
The TMC2250A operates from a single +5V supply.
All pins must be connected.
The TMC2250A operates from a single +5V supply.
All pins must be connected.
GND
Clock
CLK
D11
88
System Clock
The TMC2250A operates from a single system clock
input. All timing specifications are referenced to the
rising edge of clock.
Controls
MODE
1,0
B4, A4
112, 113
Mode Control
The TMC2250A will switch to the configuration
selected by the user (as shown in Table 3) on the
next clock. This registered control is usually static;
however, should the user wish to switch between
modes, the internal pipeline latencies of the device
must be taken into account. Valid data will not be
available at the outputs in the new configuration until
enough clocks in the new mode have passed to flush
the internal registers.
Data presented to the coefficient input ports (KA, KB,
and KC) will update three of the internal coefficient
storage registers, as indicated by the simultaneous
Coefficient Write Enable select, on the next clock.
See Table 4 and the Functional Block Diagram.
CWE
1,0
J12, J13
70, 71
Coefficient
Write Enable
Input/Output
A
11-0
E11, D13, E12,
E13, F11, F12,
F13, G13,
G11, G12,
H13, H12
B10, A11, B11,
C10, A12, B12,
C11, A13,
C12, B13,
C13, D12
A5, C6, B6, A6,
A7, B7, A8, B8,
A9, B9, A10,
C9
84, 83, 82, 81,
80, 79, 78, 77,
76, 75, 74, 73
Data Input A
Data presented to the 12-bit registered data input
ports A, B, and C are latched into the multiplier input
registers for the currently selected configuration
(Table 3). In all modes except Mode 00, new data are
internally right-shifted to the next filter tap on each
rising edge of CLK.
B
11-0
97, 96, 95, 94,
93, 92, 91, 90,
89, 87, 86, 85
Data Input B
C
11-0
111, 110,
109, 108,
107, 105,
104, 103,
101, 100, 99,
98
Data Input C
相關PDF資料
PDF描述
TMC2250AH5C3 Matrix Multiplier 12 x 10 bit, 50 MHz
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