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參數(shù)資料
| 型號(hào)： | TMC2249AH6C1 |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | Circular Connector; No. of Contacts:13; Series:MS27473; Body Material:Aluminum; Connecting Termination:Crimp; Connector Shell Size:10; Circular Contact Gender:Pin; Circular Shell Style:Straight Plug; Insert Arrangement:10-35 RoHS Compliant: No |
| 中文描述： | 12-BIT, DSP-MIXER, CPGA120 |
| 封裝： | MPGA-120 |
| 文件頁(yè)數(shù)： | 11/18頁(yè) |
| 文件大?。?/td> | 138K |
| 代理商： | TMC2249AH6C1 |
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TMC2249A
PRODUCT SPECIFICATION
REV. 1.0.2 7/6/00
11
Once all of the products of the desired taps have been
summed, the result is available at the output. The user then
"pushes" a new time-data sample on to the appropriate even
or odd data register "stack" and reiterates the summation.
Note that the coefficient bank "pointers", the BDEL and
DDEL delay words, are alternately incremented and decre-
mented on successive filter passes to maintain alignment
between the incoming data samples and their respective
coefficients.
The effective filter speed is calculated by dividing the clock
rate by one-half the number of taps implemented.
Alternatively, non-symmetric FIR filters can be implemented
using the TMC2249A in a similar fashion. Here, a shift reg-
ister is used to delay the incoming data fed to the A input by
an amount equal to one-half the length of the filter (the
length of the A delay register).
As shown in Figure 5, the data is then sent to the C input,
thus "stacking" the A and C delay registers to create a single
N-tap FIR filter. The incremented delay words (ADEL-
DDEL) for all four inputs are identical. Again, the filter
throughput is equal to the clock speed divided by one-half
the number of taps implemented.
Figure 5. Non-Symmetric 32-Tap FIR Filtering Using the
TMC2249A
TMC2011A
16-Stage Shift Register
Filter Output
A
B
C
D
x(m+0)
x(m)
h(0)
x(m+16)
h(16)
x(m+15)
h(15)
x(m+31)
TMC2249A
S
15-0
h(31)
Table 4. FIR Filtering
–
Operation Sequence
Notes:
1. If only the 16 MSBs of the result are used, the user may leave RND HIGH and SWAP low. If the 16 LSBs or all 24 bits of the
result are used, then RND should be set low.
2.
Cycle
Push
A
B
Push
C
D
ADEL
CDEL
BDEL
DDEL
ACC
ENA
ENB
ENC
END
Convolutional Sum
Resultant
Output
1
–
–
–
–
0
0
0
0
L
H
H
H
H
x(31)
h(0)+x(30)
h(1)
+x(29)
h(2)+x(28)
h(3)
+x(27)
h(4)+x(26)
h(5)
+x(25)
h(6)+x(24)
h(7)
+x(23)
h(8)+x(22)
h(9)
+x(21)
h(10)+x(20)
h(11)
+x(19)
h(12)+x(18)
h(13)
+x(17)
h(14)+x(16)
h(15)
+x(15)
h(15)+x(14)
h(14)
+x(13)
h(13)+x(12)
h(12)
+x(11)
h(11)+x(10)
h(10)
+x(9)
h(9)+x(8)
h(8)
+x(7)
h(7)+x(6)
h(6)
+x(5)
h(5)+x(4)
h(4)
+x(3)
h(3)+x(2)
h(2)
+x(1)
h(1)+x(0)
h(0)
+x(31)
h(1)+x(32)
h(0)
+x(29)
h(3)+x(30)
h(2)
+x(27)
h(5)+x(28)
h(4)
+x(25)
h(7)+x(26)
h(6)
+x(23)
h(9)+x(24)
h(8)
See Note 2
2
–
–
–
–
1
1
1
1
H
H
H
H
H
3
–
–
–
–
2
2
2
2
H
H
H
H
H
4
–
–
–
–
3
3
3
3
H
H
H
H
H
5
–
–
–
–
4
4
4
4
H
H
H
H
H
6
–
–
–
–
5
5
5
5
H
H
H
H
H
7
–
–
–
–
6
6
6
6
H
H
H
H
H
8
–
–
–
–
7
7
7
7
H
H
H
H
H
9
–
–
–
–
8
8
8
8
H
H
H
H
H
10
–
–
–
–
9
9
9
9
H
H
H
H
H
11
–
–
–
–
A
A
A
A
H
H
H
H
H
12
–
–
–
–
B
B
B
B
H
H
H
H
H
13
–
–
–
–
C
C
C
C
H
H
H
H
H
14
–
–
–
–
D
D
D
D
H
H
H
H
H
15
–
–
–
–
E
E
E
E
H
H
H
H
H
16
–
–
x(32)
–
F
F
F
F
H
H
H
L
H
17
–
–
–
–
0
0
F
F
H
H
H
H
H
18
–
–
–
–
1
1
E
E
H
H
H
H
H
19
–
–
–
–
2
2
D
D
H
H
H
H
H
20
–
–
–
–
3
3
C
C
H
H
H
H
H
21
–
–
–
–
4
4
B
B
H
H
H
H
H
s
x k
h k
x k
16
+
)
h k
+
(
)
K
0
=
15
∑
=
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