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參數(shù)資料
| 型號(hào)： | TMC2242CKTC |
| 廠(chǎng)商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類(lèi)： | 數(shù)字信號(hào)處理外設(shè) |
| 英文描述： | Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz |
| 中文描述： | 12-BIT, DSP-DIGITAL FILTER, PQFP44 |
| 封裝： | MQFP-44 |
| 文件頁(yè)數(shù)： | 4/16頁(yè) |
| 文件大?。?/td> | 89K |
| 代理商： | TMC2242CKTC |
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PRODUCT SPECIFICATION
TMC2242C
4
Pin Descriptions
Pin Name
Dedicated Timing Controls
CLK
Pin Number
PLCC
Pin Function Description
MQFP
42
36
Clock
edges all timing parameters are referenced. All internal registers are strobed on
every rising edge of CLK, although the output register is strobed on alternate
rising edges during decimation. In all modes, the frequency applied to CLK is the
higher of the input and output data sampling rates. During interpolation, the chip
reads its input bus on alternate rising edges of CLK.
Synchronization
. During interpolation, the chip accepts input data on alternate
rising edges of CLK and inserts zeroes on the remaining cycles. If SYNC is
HIGH during CLK rising edge 0 and LOW during CLK rising edge 1, the chip will
accept data on CLK 1 and insert a zero on CLK 2. Thereafter, if SYNC is either
held LOW or fed a square wave of half the CLK frequency, the part will continue
to accept data on odd-numbered CLK edges and to stuff zeroes on even-
numbered edges. Similarly, during decimation, the output data change only on
alternate clock cycles. If the user operates SYNC as above, each even-
numbered rising edge of CLK will trigger a change in the output. In all other
modes, the state of SYNC doesn’t affect operation of the chip.
. The chip operates from a single-phase master clock, to whose rising
SYNC
43
37
Dedicated Data Input Port
SI
11-0
40,
37-30,
27-25
34,
31-24,
21-19
Input Data
the rising edges of CLK. SI
. A 12-bit two’s complement or unsigned input word is registered by
0
is the LSB.
Dedicated Data Output Port
SO
15-0
4-11,
14-21
42-44,
1-5,
8-15
Output Data MSBs
output emerge here, following each rising edge of CLK. The format may be two’s
complement, unsigned, or inverted offset binary. Bits SO
input bits SI
11-0
, respectively. An on-chip limiter prevents overflows and
underflows in the output data.
Dual Function Data Output/Control Input Pins
SO
3-2
Output Data
. These pins serve as data outputs when RND
RND
2
is HIGH, they become additional filter mode controls (Table 1).
SO
1
Output Data 2
LSB.
This pin is a data output when RND
either RND
2
or RND
1
is HIGH, it becomes an additional rounding control.
SO
0
Output Data LSB
. This pin is a data output if and only if all RND bits are LOW.
Otherwise, it augments the data I/O format controls.
Dedicated Static Controls (Set state before first desired data input.)
INT, DEC
44, 1
38, 39
Interpolate and Decimate.
overall operating mode, as discussed earlier in Table 1
TCO
2
40
Output format control.
complement format. When TCO is LOW, they are inverted offset binary, unless
SO
0
is HIGH and RND is nonzero, in which case they are unsigned.
RND
2-0
22-24
16-18
Round and output tristate.
width 8-16 bits. All outputs at and below the rounding bit position are tristated,
allowing the 4 LSBs to become control inputs.
Active, Asynchronous Control
OE
3
41
Output enable.
LOW activates output bus from SO
as chosen by RND
2-0
. All drivers at and below the rounding point are disabled,
as are all drivers when OE is HIGH.
. When OE is LOW, the 12 most significant bits of the filter’s
15-4
correspond to
2
is LOW. When
nd
2-1
are LOW. When
1
2
Jointly with SO
3-2
, these bits select the chip’s
When TCO is HIGH, the output data are in two’s
Selects output rounding position and active bus
15
down to the effective LSB,
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC2242CKTC1 | 制造商:FAIRCHILD 制造商全稱(chēng):Fairchild Semiconductor 功能描述:Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz |
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| TMC2242CR2C1 | 制造商:FAIRCHILD 制造商全稱(chēng):Fairchild Semiconductor 功能描述:Digital Half-Band Interpolating/Decimating Filter 12-bit In/16-bit Out, 60 MHz |
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