參數(shù)資料
型號(hào)： TMC22153AKHC
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： JT 32C 32#20 SKT PLUG
中文描述： COLOR SIGNAL DECODER, PQFP100
封裝： MQFP-100
文件頁(yè)數(shù)： 8/84頁(yè)
文件大?。?/td> 417K
代理商： TMC22153AKHC
TMC22x5yA
PRODUCT SPECIFICATION
8
REV. 1.0.0 2/4/03
Control Register Map
The TMC22x5yA is initialized and controlled by a set of
registers which determine the operating modes.
An external controller is employed to write and read the
Control Registers through either the 8-bit parallel or 2-line
serial interface port. The parallel port, D
7-0
, is governed by
pins CS, R/W, and A
1-0
. The serial port is controlled by SDA
and SCL.
Reg
Bit
Name
Function
Global Control
00
00
00
00
00
7
6
SRST
HRST
SET
DHVEN
STD
Input Processor Control
Software reset
Hardware reset
SET pin function
Output H&V sync enable
Selects video standard
5-3
2
1-0
01
01
01
01
01
01
01
01
7
6
5
4
3
2
1
0
reserved, set to zero
Input mux control
8 bit input format
TRS detect enable
TRS blank enable
Chroma input msb invert
AB mux control
Input clock rate select
Burst Loop Control
BLLRST
BLL auto. reset enable
VIPEN
Video Input Processor
enable
LOCK
Global lock mode
BLM
BLL lock mode
KILD
Color kill disable
DMODBY
Demod bypass
CINT
C
B
C
R
interpolation enable
Chroma Processor Control
BLFS
Burst loop filter select
CCEN
Chroma coring enable
CCOR
Chroma coring threshold
GAUBY
Gaussian filter bypass
GAUSEL
Gaussian filter select
Burst Threshold
BTH
Burst threshold
Pedestal
PED
Pedestal level
IPMUX
IP8B
TDEN
TBLK
IPCMSB
ABMUX
CKSEL
02
02
7
6
02
02
02
02
02
5-4
3
2
1
0
03
03
03
03
03
7-5
4
3-2
1
0
04
7-0
05
7-0
Luma Processor Control
06
06
06
06
06
06
7-6
5
4
3-2
1
0
reserved, set to zero
Adaptive notch enable
Adaptive notch rounding
Adaptive notch threshold
Adaptive notch select
Notch enable
ANEN
ANR
ANT
ANSEL
NOTCH
Comb Processor Control
LS1BY
LS1IN
LS2DLY
SPLIT
BSFBY
BSFSEL
BSFMSB
07
07
07
07
07
07
07
7
6
5
4
3
2
1
Line store 1 bypass
Line store 1 input
Line store 2 delay
Line store 2 data width
Bandsplit filter bypass
Bandsplit filter select
Inverts msb of bandsplit
filter
Delays input to GRS
decode by 1H
Mid-Sync Level
Mid-sync level
Extended DRS
PCKF
Clock rate
VSTD
Video standard
Output Control
OP8B
Output rounded to 8 bits
OPLMT
Output limit select
MSEN
Mixed sync enable
OPCMSB
Chroma output msb invert
YBAL
Luma color correction
BUREN
Output burst enable
FMT422
Enables C
B
C
R
output mux
CDEC
C
B
C
R
decimation enable
YUVT
Enables D1 output
reserved, set to zero
DRSEN
DRS output enable
DRSCK
DRS data rate
Comb Filter Control
ADAPT
Adaption mode
YCES
YC input error signal
control
YCSEL
luma/chroma comb filter
select
COMB
Comb filter architecture
07
0
GRSDLY
08
7-0
MIDS
09
09
7-4
3-0
0A
0A
0A
0A
0A
0A
0B
0B
0B
0B
0B
0B
7
6-5
4-3
2
1
0
7
6
5
4-2
1
0
0C
0C
7-6
5
0C
4
0C
3-0
Reg
Bit
Name
Function
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