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參數(shù)資料
| 型號： | TMC22091R0C |
| 廠商： | FAIRCHILD SEMICONDUCTOR CORP |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | Digital Video Encoders/Layering Engine |
| 中文描述： | COLOR SIGNAL ENCODER, PQCC84 |
| 封裝： | PLASTIC, LCC-84 |
| 文件頁數(shù)： | 32/60頁 |
| 文件大?。?/td> | 293K |
| 代理商： | TMC22091R0C |
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TMC22091/TMC22191
PRODUCT SPECIFICATION
32
VITS Insertion
In both NTSC and PAL, the TMC22x91 can be set up to
allow Vertical Interval Test Signals (VITS) in the vertical
interval in place of normal black burst lines (UBB). This is
controlled by Interface Control Register bit 7. If this bit is
LOW, UBB lines are black burst and are independent of
TMC22x91 input data. If the bit is HIGH, all vertical interval
UBB lines become UVV. UVV lines are active video and
depend upon data input to the TMC22x91. VITS lines may
carry special test signals or pass captioning data through the
encoder.
Edge Control
SMPTE 170M NTSC and Report 624 PAL video standards
call for specific rise and fall times on critical portions of the
video waveform. The TMC22x91 does this automatically.
The TMC22x91 digitally defines slopes compatible with
SMPTE 170M NTSC or CCIR Report 624 PAL on:
1.
H and V Sync leading and trailing edges.
2.
Burst envelope.
3.
Active video leading and trailing edges.
Subcarrier Programming
The color subcarrier is produced by an internal 32-bit digital
frequency synthesizer which is completely programmable in
frequency and phase. Separate registers are provided for phase
adjustment of the color burst and of the active video, permit-
ting external delay compensation and color adjustment.
In Master or Slave mode, the subcarrier is internally syn-
chronized to establish and maintain a specified relationship
between the falling edge of horizontal sync and color burst
phase (SCH). In NTSC and PAL, SCH synchronization is
performed every eight fields, on field 1 of the eight-field
sequence. Proper subcarrier phase is maintained through the
entire eight fields, including the 25 Hz offset in PAL
systems. See the description of 8FSUBR under Test Control
Register bit 1 for the subcarrier reset function.
In Genlock mode, the phase and relative frequency of the
incoming video are transmitted by the TMC22071 Genlock-
ing Video Digitizer over the CVBS bus at the beginning of
each line, which synchronize the digital subcarrier synthe-
sizer. When key control register bit BUKEN is HIGH and
digitized burst from the TMC22071 is passed through to the
reconstruction D/A converter, the reference subcarrier for the
chrominance modulator is still synthesized within the
encoder.
Table 12. Standard Timing Parameters
Notes:
1. XBP, VA, VC,
and VB are 10-bit values. The 2 MSBs for these four variables are in Timing Register 18. See Table 3.
2. EH and SL are 9-bit values. A most significant "1" is forced by the TMC22x91 since EH and SL must range from 256 to 511.
EH and SL may be extended to 767. Only the eight LSBs are stored in Timing Registers 1B and 1C.
3. Every calculated timing parameter has a minimum value of 5 except EH and SL which have minimum values of 256.
Standard
Field
Rate
(Hz)
Horizontal
Freq.
(kHz)
Pixel
Rate
(Mpps)
PXCK
Freq.
(MHz)
Timing Register (hex)
SY
10
BR
11
BU
12
CBP
13
XBP
14
VA
15
VC
16
VB
17
Note 1
18
FP
19
EL
1A
EH
2
1B
SL
2
1C
SH
1D
CBL
1E
NTSC sqr.
pixel
59.94 15.734266
12.27
24.54
3A
07
1F
0F
23
8B
05
77
65
12
1C
6A
4C
3A
52
NTSC
CCIR-601
59.94 15.734266
13.50
27.00
40
08
22
13
3F
CA
1D
9D
65
13
1F
8E
6E
3F
59
NTSC 4x
F
SC
PAL sqr.
pixel
59.94 15.734266
14.32
28.64
43
09
24
12
54
F7
30
B5
65
15
21
A6
84
43
5F
50.00 15.625000
14.75
29.50
45
0D
21
21
6D
03
2B
B7
75
19
23
B5
93
45
61
PAL
CCIR-601
50.00 15.625000
13.50
27.00
40
0C
1E
22
4D
BE
0E
93
65
16
20
90
71
3F
58
PAL 15
Mpps
50.00 15.625000
15.00
30.00
46
0D
22
21
73
11
31
BF
75
19
23
BD
9A
47
62
PAL-M
sqr.pixel
60.00 15.750000
12.50
25.01
3E
0B
1C
13
26
86
FE
8B
61
18
1D
70
53
3A
52
PAL-M
CCIR-601
60.00 15,750000
13.50
27.00
44
0C
1E
13
26
Bf
12
99
65
1A
1F
8E
6E
3F
57
PAL-M 4x
F
SC
60.00 15,750000
14.30
28.60
47
0D
20
15
4C
E8
22
AC
65
1B
21
A5
84
42
5D
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| TMC22191R0C | Digital Video Encoders/Layering Engine |
| TMC22091 | Digital Video Encoders(數(shù)字視頻編碼器) |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| TMC22091R0CT | 功能描述:視頻 IC D/V Encoder Layering Engine RoHS:否 制造商:Fairchild Semiconductor 工作電源電壓:5 V 電源電流:80 mA 最大工作溫度:+ 85 C 封裝 / 箱體:TSSOP-28 封裝:Reel |
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| TMC22151AKHC | 制造商:CADEKA 制造商全稱:CADEKA 功能描述:Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
| TMC22151KHC | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| TMC22152AKHC | 制造商:FAIRCHILD 制造商全稱:Fairchild Semiconductor 功能描述:Multistandard Digital Video Decoder Three-Line Adaptive Comb Decoder Family, 8 & 10 bit |
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