參數(shù)資料
型號(hào)： TMC2193
廠商： Fairchild Semiconductor Corporation
英文描述： 10 Bit Encoder
中文描述： 10位編碼器
文件頁(yè)數(shù)： 7/72頁(yè)
文件大小： 448K
代理商： TMC2193
PRODUCT SPECIFICATION
TMC2193
REV. 1.0 3/26/03
7
Functional Description
Input Formats
Control Registers for this section
The TMC2193 supports both RGB and YC
B
C
R
component
sources on the pixel data port. For RGB sources the
TMC2193 will accept a 24 bit RGB source with a sample
rate of 4:4:4. YC
B
C
R
input sources are supported in 10 bit
4:2:2, 20 bit 4:2:2, 20 bit 4:4:4, and 24 bit 4:4:4. In the 4:2:2
cases the color difference components are linearly interpo-
lated to 4:4:4 internally.
Demuxing of multiplexed data streams depends on which
synchronization mode the encoder is operating in. For slave
and genlock modes the falling edge of HSIN must be LOW
prior to the C
B
data in order to demux the data correctly. For
master mode synchronization the falling edge of HSOUT
must be LOW prior to the Y data in order to demux the data
correctly. Finally, in 656 mode the demuxing of the data
stream is determined by the TRS codes, the first sample after
the TRS is considered a C
B
sample of the C
B
Y C
R
Y
I
packet.
The control register D1OFF controls the formatting of the
incoming luminance data at the pixel data port. When
D1OFF is HIGH a blanking level of 64
10
is subtracted from
the luminance and when D1OFF is LOW the incoming the
pixel data is passed through. The inversion of the MSB’s on
the C
B
and C
R
components is controlled by the INMODE
control register.
Figure 1. Input Formats
1.
INMODE = 000 or 100, PD[7:0] = Y/G, PD[23:16] = C
B
/B, PD[15:8] = C
R
/R
Figure 2. 24 Bit Input Format
Address
0x05
0x05
0x06
Bit(s)
7
6-4
0
Name
D1OFF
INMODE
TSOUT
INMODE
x00
101
110
111
0
0
2
2
65-6294-02
23
7
9
9
9
PD
C
B
/BLUE
C
R
/RED
Y/GREEN
0
7
16
15
7
YC
B
C
R
C
B
C
R
C
B
C
R
0
0
0
14
1
1
9
0
0
0
7
8
9
9
Y
Y
t
DO
PD[7:0]
PD[15:8]
PD[23:16]
PXCK
HSOUT
(TSOUT = 1)
65-6294-03
(Y/G)
n-1
(C /R)
n-1
(C /B)
n-1
(Y/G)
x+1
(Y/G)
x+2
(Y/G)
x
(Y/G)
n
(Y/G)
0
(C /R)
n
(C /R)
0
(C /B)
n
(C /B)
0
t
S
t
H
t
DO
x = (SY+BR+BU+CBP)*2
128
0
n = (SY+BR+BU+CBP+AV)*2
HSIN
t
SP
(C /B)
x
(C /B)
x+1
(C /B)
x+2
(C /R)
x
(C /R)
x+1
(C /R)
x+2
2.
INMODE = 101, PD[23:14] = YC
B
C
R
running at 27MHz.
The PD port is clocked at twice the pixel rate, with the data
organized as C
B
Y C
R
Y, with the cosited Y's following the
C
B
's. In its CCIR-656 time base mode, the demuxed C
B
, Y,
and C
R
data is synchronized to the SAV preamble. The first
data value, after the SAV preamble, is treated as a C
B
data
point in the multiplexed C
B
, Y, C
R
Y , D1 data stream.
Note: Figure 3, pixel numbering, reflects the SMPTE-125M
pixel numbering.
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