參數(shù)資料
型號： TMC2192KHC
廠商： FAIRCHILD SEMICONDUCTOR CORP
元件分類： 顏色信號轉換
英文描述： 10 Bit Encoder
中文描述： COLOR SIGNAL ENCODER, PQFP100
封裝： MQFP-100
文件頁數(shù)： 5/69頁
文件大?。?/td> 457K
代理商： TMC2192KHC
PRODUCT SPECIFICATION
TMC2192
REV. 1.0.0 8/13/03
5
PXCK
95
TTL
Pixel Clock Input.
PXCK is a clock signal that period is twice
the sample rate of the pixel data. The operating range is 20 to
30 MHz. The clock is internally divided by 2 to generate the
internal pixel clock, PCK. PXCK drives the entire TMC2192
except the asynchronous microprocessor interface.
Master Chip Reset.
When LOW, All outputs are tri-stated and
the internal state machines and control registers are reset. At
rising edge of RESET, all outputs are active, the preset values
will be loaded into the control registers and the internal states
machines start to operate.
Vertical Sync Input.
When operating in slave, Genlock, or
DRS-Lock the TMC2192 will start a new vertical field with each
falling edge of VSIN that is coincident with HSIN.
RESET
94
TTL
VSIN
55
TTL
SYNC & CONTROL OUTPUTS (11 pins)
FLD[2:0]
81
–
83
TTL
Field Identifier.
Field Identifier outputs the current field number.
For all video standards the field identifier will cycle through the
eight counts.
Horizontal Sync Output.
The alignment of HSOUT to the pixel
data port or DCVBS port is controlled by control register
TSOUT.
Vertical Blanking Interval Line Identifier.
LINE identifies the
current line number for the first 31 lines. If the line count is
greater than 31 then LINE is 11111b. The first line with a vertical
serration is considered to be line 0.
Pixel Data Control.
HSOUT
74
TTL
LINE[4:0]
76
–
80
TTL
PDC
73
TTL
When PDCDIR = LOW:
At a rising edge, The next pixel starts a
controlled ramp of the PD data. At a falling edge, the pixel prior
is the last PD used in the ramp. The rising edge is determined
by the PDCCNT control register, the falling edge of PDC is
determined by the horizontal timing registers.
When PDCDIR = HIGH:
PDCIN is used to override the internal
PDC. When HIGH, the internal PDC controls the blank and
unblank window. When LOW, the video remains blanked
regardless of the internal PDC. All edges have the same ramp
control as the internal PDC.
Vertical Sync Output.
The alignment of VSOUT to the pixel
data port or DCVBS port is controlled by control register
TSOUT.
VSOUT
75
TTL
DATA INPUTS (39 pins)
CVBS[9:0]
OL[4:0]
PD[23:0]
ANALOG INTERFACE – Video Out (5 pins)
LUMA
CHROMA
COMP
84
–
93
21
–
25
TTL
TTL
TTL
Composite Data Input
Overlay Control
Component Data Input
27
–
38, 41
–
52
10
5
2
1.35Vp-p
1.35Vp-p
1.35Vp-p
Luma
Chroma
Composite D/A with optional keying
Pin Definitions
(continued)
Pin Name
Pin Number
Value
Description
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