參數(shù)資料
型號: TMC2072
廠商: Fairchild Semiconductor Corporation
英文描述: Genlocking Video Digitizer
中文描述: 同步鎖相視頻數(shù)字化儀
文件頁數(shù): 13/21頁
文件大?。?/td> 160K
代理商: TMC2072
PRODUCT SPECIFICATION
TMC2072
REV. 1.0.4 6/19/01
13
CVBS Bus Data Formats
The CVBS bus outputs a Genlock Reference Signal (GRS)
along with the 8-bit digital composite video data. The range
of output data versus video input voltage is illustrated in
Figure 6 where sync tip and blanking levels are controlled by
the digital backporch clamp of the TMC2072. During hori-
zontal sync, the TMC2072 outputs field identification, sub-
carrier frequency, and subcarrier phase information on the
CVBS bus.
Figure 6. Output Data vs. Input Video Level
Peak Chrominance
Peak Luminance
Back Porch
Burst
65-2072-08
Blanking
Sync Tip
NTSC
FEh
PAL-M
PAL
FFh
D2h
CFh
3Ch
40h
03h
03h
Field identification is output on CVBS
2-0
. The LSB,
CVBS
0
, will be LOW during odd fields and HIGH for even
fields. When NTSC operation is selected, CVBS
1-0
count
00,01,10,11 for fields 1 through 4 respectively. When PAL
operation is selected, CVBS
2-0
count 000, 001, 010, etc. to
111 for fields 1 through 8, respectively.
CVBS
3
indicates V-component inversion in PAL. It is HIGH
for NTSC lines (burst 135
°
) and LOW for PAL lines (burst
225
°
)
Subcarrier frequency is sent out in a 24-bit binary represen-
tation in six 4-bit nibbles on CVBS
3-0
. Subcarrier frequency,
f
23-0
, is that of the on-chip burst PLL.
Subcarrier phase,
Φ
23-0
, is also sent out in a 24-bit binary
representation in six 4-bit nibbles on CVBS
3-0
. Bit
Φ
23
is
the MSB.
Figure 7. Genlock Reference Signal (GRS) Format
Figure 8. CVBS Bus Video Data Format
PXCK
0
1
PIXEL
PIXEL
PIXEL
FID
FIELD IDENTIFICATION
FREQUENCY
PHASE
PIXEL
PIXEL
65-2072-09
f
23:20
f
19:16
f
15:12
f
11:8
f
7:4
f
3:0
φ
23:20
φ
19:16
φ
15:12
φ
11:8
φ
7:4
φ
3:0
2
3
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
GHSYNC
CVBS3:0
PXCK
65-2072-10
PIXEL 0
PIXEL 1
LDV
CVBS7:0
tHO
tXL
tDO
tXV
tPWHPX
tPWHPX
1/fPXCK
GHSYNC
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