參數(shù)資料
型號(hào): TMC1273
廠商: Fairchild Semiconductor Corporation
英文描述: 8 bit, 20 Msps, 3V Power Supply Video A/D Converter(8位,20Msps, 3V 電源視頻A/D轉(zhuǎn)換器)
中文描述: 8位,20 MSPS的3V的電源供應(yīng)器視頻A / D轉(zhuǎn)換器(8位,20Msps,3V的電源視頻的A / D轉(zhuǎn)換器)
文件頁(yè)數(shù): 3/20頁(yè)
文件大小: 98K
代理商: TMC1273
TMC1173A/TMC1273
PRODUCT SPECIFICATION
3
P
Table 1. Output Coding
Notes:
1. LSB = (R
T
– R
B
) / 255
2. TMC1273 Only
Digital Inputs and Outputs
Sampling of the applied input signal takes place on the fall-
ing edge of the CONV signal (Figure 2). The output word is
delayed by 2 1/2 CONV cycles. It is then available after the
rising edge of CONV. The previous data on the output
remain valid for t
HO
(Output Hold Time), satisfying any
hold time requirement of the receiving circuit. The new data
become valid t
DO
(Output Delay Time) after this rising edge
of CONV.
Whenever the analog input signal is sampled and found to be
at a level beyond the A/D conversion range, an Overrange
output of the TMC1273 will go HIGH. If the input is more
positive (by at least one LSB) than the positive end of the
range, ORP will go HIGH and D
7-0
will be FFh. If the input
is more negative (by at least one LSB) than the negative end
of the range, ORN will go HIGH and D
7-0
will be 00h.
The outputs of the TMC1173A/1273 are CMOS- and 3V
TTL-compatible, and are capable of driving four low-power
Schottky TTL (54/74LS) loads. An Output Enable control,
OE, places the outputs in a high-impedance state when
HIGH. The outputs are enabled when OE is LOW.
Power and Ground
The TMC1173A/1273 operates from a single +2.7 to +3.6
Volt power supply. For optimum performance, it is recom-
mended that A
GND
and D
GND
pins of the TMC1173A/1273
be connected to the system analog ground plane.
Input Voltage
R
T
+ 1 LSB
R
T
R
T
– 1 LSB
R
B
+ 128 LSB
R
B
+ 127 LSB
R
B
+ 1 LSB
R
B
R
B
– 1 LSB
ORP
2
1
0
0
0
0
0
0
0
ORN
2
0
0
0
0
0
0
0
1
Output
FF
FF
FE
80
7F
01
00
00
Figure 2. Conversion Timing
CONV
D
7-0
ORP
ORN
OE
V
IN
65-1173A-03
Data N–3
Data N–2
Data N–1
Data N
tSTO
t
PWL
t
HO
t
DIS
t
ENA
t
DO
t
PWH
1/f
S
Hi-Z
Sample N
Sample N+1
Sample N+2
Sample N+3
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