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參數(shù)資料
| 型號： | TMC1203KLC50 |
| 廠商： | RAYTHEON SEMICONDUCTOR |
| 元件分類： | ADC |
| 英文描述： | Triple Video A/D Converter |
| 中文描述： | TRIPLE 1-CH 8-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP80 |
| 文件頁數(shù)： | 2/16頁 |
| 文件大小： | 88K |
| 代理商： | TMC1203KLC50 |
TMC1203
PRODUCT SPECIFICATION
2
Circuit Function
Within the TMC1203 are three 8-bit A/D converters, each
employing two-step architecture to convert an analog input
to a digital output at rates up to 50 Msps. Input signals are
held in integral track/hold stages during the conversion pro-
cess. Operation is pipelined, with one input sample taken and
one output word provided for each CLK
X
cycle.
Each of the three converters function identically. In the fol-
lowing descriptions ‘X’ refers to a generic input/output or
clock where ‘X’ is equivalent to A, B or C.
The first step in the conversion process is a coarse 4-bit
quantization. This determines the range of the subsequent
fine 4-bit quantization step. To eliminate spurious codes, the
fine 4-bit A/D quantizer output is gray-coded and converted
to binary before it is combined with the coarse result to form
a complete 8-bit result.
Analog Input and Voltage References
Each A/D accepts analog signals in the range R
digital data. Input signals outside this range produce “satu-
rated” 00h or FFh output codes. The device will not
be damaged by signals within the range A
BX
to R
TX
into
GND
to V
DDA
.
Input range is very flexible and extends from the +5 Volt
power supply to ground. Nominal input range is 2 Volts,
extending from 0.6V to 2.6V. Characterization and
performance is specified over this range. However, the
part will function with a full-scale range from 1.0V to 5.0V.
A smaller input range may simplify analog signal condition-
ing circuitry, at the expense of additional noise sensitivity
and some reduced differential linearity performance.
External voltage reference sources are connected to the R
and R
BX
pins. R
BX
can be grounded. Within each A/D con-
verter is a reference resistor ladder comprising 255 resistors
that are accessed by the TMC1203 comparators. R
nected to the top of the ladder, R
offset errors are directly related to the accuracy and stability
of the applied reference voltages.
TX
TX
is con-
BX
to the bottom. Gain and
Because a two-step conversion process is employed, it is
important that the references remain stable during the
ENTIRE conversion process (two clock cycles). The refer-
ence voltage can then be changed, but any conversion in
progress during a reference change is invalid.
Digital Inputs and Outputs
Sampling of the applied input signal occurs on the "falling"
edge of the CLK
X
signal (Figure 1). Output data is delayed
by 2 1/2 CLK
X
cycles and is valid following the "rising"
edge of CLK
X
. Previous output data remains valid for t
(Output Hold Time), satisfying any hold time requirement of
the receiving circuit. New data becomes valid t
Delay Time) after this rising edge of CLK
HO
D
(Output
X
.
Whenever the analog input signal is sampled and found to be
at a level beyond the A/D conversion range, the output limits
at 00h or FFh, as appropriate.
Table 1. A/D Output Coding
Note:
1 LSB = (R
TX
- R
BX
) / 255
The outputs of the TMC1203 are CMOS- and
TTL-compatible, and are capable of driving four low-power
Schottky TTL loads. An Output Enable control, OE
the A/D outputs in a high-impedance state when HIGH.
The outputs are enabled when OE
X
, places
X
is LOW.
Power and Ground
The TMC1203 operates from a single +5 Volt power supply.
For optimum performance, it is recommended that A
and D
GND
pins of the TMC1203 be connected to the system
analog ground plane.
GND
Input Voltage
R
TX
+ 1 LSB
R
TX
R
TX
- 1 LSB
R
BX
+ 128 LSB
R
BX
+ 127 LSB
R
BX
+ 1 LSB
R
BX
R
BX
- 1 LSB
Output
FF
FF
FE
80
7F
01
00
00
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