
PRODUCT SPECIFICATION
TMC1173A/TMC1273
2
P
Functional Description
The TMC1173A/1273 8-bit A/D converter uses a two-step 
architecture to perform analog-to-digital conversion at rates 
up to 20 Msps. The input signal is held in an integral track/
hold stage during the conversion process. Operation is pipe-
lined, with one input sample taken and one output word pro-
vided for each CONVert cycle. 
The first step in the conversion process is a coarse 4-bit 
quantization. This determines the range of the subsequent 
fine 4-bit quantization step. To eliminate spurious codes, the 
fine 4-bit A/D quantizer output is gray-coded and converted 
to binary before it is combined with the coarse result to form 
a complete 8-bit result.
The TMC1173A/1273 is characterized and specified for use 
in “3 Volt” applications where the power supply voltage can 
be as low as 2.7V.
Analog Input and Voltage References
The TMC1173A/1273 converts analog signals in the range 
R
B
 to R
T
 into digital data. Input signals outside that range 
produce “saturated” 00h or FFh output codes. The device 
will not be damaged by signals within the range A
GND
 to 
V
DDA
.
The A/D converter input range is very flexible and extends 
from the +3.3 Volt power supply to ground. The nominal 
input range is 1.56 Volts, from 0.36V to 1.92V. The circuit is 
characterized and performance is specified over that range. 
However, the part will work well with a full-scale range from 
1.0V to 3.0V. A reduced input range may simplify analog 
signal conditioning circuitry, at the expense of additional 
noise sensitivity and some reduced differential linearity per-
formance. Similarly, increasing the range can improve differ-
ential linearity, but puts a greater burden on the input signal 
conditioning circuitry.
In many applications, external voltage reference sources are 
connected to the R
T
 and R
B
 pins. R
B
 can be grounded. Gain 
and offset errors are directly related to the accuracy and 
stability of the applied reference voltages.
Two reference pull-up and pull-down resistors connected to 
VR+ and VR-, are provided internally for operation without 
external voltage reference circuitry (Figure 1). The reference 
voltages applied to R
T
 and R
B
 may be generated by connect-
ing VR+ to R
T
 and VR- to R
B
. The power supply voltage is 
divided by the on-chip resistors to bias the R
T
 and R
B
 points. 
This sets-up the converter for operation in its nominal range 
from 0.4V to 1.6V. 
Figure 1. Reference Resistors
With V
DDA
 at 3.0V, connecting VR+ to R
T
 and grounding 
R
B
 will provide an input range from 0.0V to 1.36V, while 
connecting R
T
 to V
DDA
 and R
B
 to VR- produces a full scale 
range of 2.31V referenced to V
DDA
. External resistors may 
also be employed to provide arbitrary reference voltages, but 
they will not match the temperature coefficient of the on-
chip resistors as well as R+ and R-, and will cause the con-
verter transfer function to vary with temperature. 
With this implementation, errors in the power supply voltage 
end up on the conversion data output. 
Because a two-step conversion process is employed, it is 
important that the references remain stable during the 
ENTIRE conversion process (two clock cycles). The refer-
ence voltage can then be changed, but any conversion in 
progress during a reference change is invalid.
VDDA
VR+
+3.0V
R
T
R+
324
RREF
270
R–
81
R
B
VR–
+1.56V
+0.36V
65-1173A-02