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| 型號(hào)： | TM497FBK32S-70 |
| 廠商： | Texas Instruments, Inc. |
| 英文描述： | EXTENDED DATA OUT DYNAMIC RAM MODULES |
| 中文描述： | 擴(kuò)展數(shù)據(jù)輸出動(dòng)態(tài)隨機(jī)存儲(chǔ)器模塊 |
| 文件頁(yè)數(shù)： | 6/9頁(yè) |
| 文件大?。?/td> | 118K |
| 代理商： | TM497FBK32S-70 |
TM497BBK32, TM497BBK32S
4194304 BY 32-BIT
DYNAMIC RAMMODULE
SMMS433B – JANUARY 1993 – REVISED JUNE 1995
6
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251–1443
capacitance over recommended ranges of supply voltage and operating free-air temperature,
f = 1 MHz (see Note 5)
PARAMETER
MIN
MAX
UNIT
Ci(A)
Ci(R)
Ci(C)
Ci(W)
Co(DQ)
NOTE 5: VCC = 5 V
±
0.5 V, and the bias on pins under test is 0 V.
Input capacitance, address inputs
40
pF
Input capacitance, RAS inputs
28
pF
Input capacitance, CAS inputs
14
pF
Input capacitance, write-enable input
56
pF
Output capacitance on DQ pins
7
pF
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature
PARAMETER
’497BBK32-60
MIN
’497BBK32-70
MIN
’497BBK32-80
MIN
UNIT
MAX
MAX
MAX
tAA
tCAC
tCPA
tRAC
tCLZ
tOH
tOFF
NOTE 6: tOFF is specified when the output is no longer driven.
Access time from column address
30
35
40
ns
Access time from CAS low
15
18
20
ns
Access time from column precharge
35
40
45
ns
Access time from RAS low
60
70
80
ns
CAS to output in low-impedance state
0
0
0
ns
Output disable time from start of CAS high
3
3
3
ns
Output disable time after CAS high (see Note 6)
0
15
0
18
0
20
ns
timing requirements over recommended ranges of supply voltage and operating free-air
temperature
’497BBK32-60
MIN
’497BBK32-70
MIN
’497BBK32-80
MIN
UNIT
MAX
MAX
MAX
tRC
tPC
tRASP
tRAS
tCAS
tCP
tRP
tWP
tASC
tASR
tDS
tRCS
tCWL
tRWL
tWCS
tWRP
NOTES:
Cycle time, random read or write (see Note 7)
110
130
150
ns
Cycle time, page-mode read or write (see Notes 7 and 8)
40
45
50
ns
Pulse duration, page-mode, RAS low
60
100 000
70
100 000
80
100 000
ns
Pulse duration, non-page-mode, RAS low
60
10 000
70
10 000
80
10 000
ns
Pulse duration, CAS low
15
10 000
18
10 000
20
10 000
ns
Pulse duration, CAS high
10
10
10
ns
Pulse duration, RAS high (precharge)
40
50
60
ns
Pulse duration, W low
10
10
10
ns
Setup time, column address before CAS low
0
0
0
ns
Setup time, row address before RAS low
0
0
0
ns
Setup time, data before CAS low
0
0
0
ns
Setup time, W high before CAS low
0
0
0
ns
Setup time, W-low before CAS high
15
18
20
ns
Setup time, W-low before RAS high
15
18
20
ns
Setup time, W-low before CAS low
0
0
0
ns
Setup time, W-high before RAS low (CBR refresh only)
10
10
10
ns
7. All cycles assume tT = 5 ns.
8. To assure tPC min, tASC should be
≥
tCP.
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